diff --git a/5_SC1_KC2_TC/Makefile b/5_SC1_KC2_TC/Makefile new file mode 100644 index 0000000..dabb148 --- /dev/null +++ b/5_SC1_KC2_TC/Makefile @@ -0,0 +1,56 @@ +SRC_PATH = src +BUILD_DIR = build +VHDL_SRCS = \ + $(SRC_PATH)/xtime.vhd \ + $(SRC_PATH)/xxtime.vhd \ + $(SRC_PATH)/texpand.vhd \ + $(SRC_PATH)/circ_mult.vhd \ + $(SRC_PATH)/shiftrows.vhd \ + $(SRC_PATH)/enc.vhd \ + $(SRC_PATH)/sboxed.vhd \ + $(SRC_PATH)/sbox.vhd \ + $(SRC_PATH)/reg.vhd \ + $(SRC_PATH)/kreg.vhd \ + $(SRC_PATH)/mixcolumn.vhd \ + $(SRC_PATH)/mixcol.vhd \ + $(SRC_PATH)/mux128.vhd \ + $(SRC_PATH)/andmask.vhd \ + $(SRC_PATH)/keygen.vhd \ + $(SRC_PATH)/ishiftrows.vhd \ + $(SRC_PATH)/invmixcol.vhd \ + $(SRC_PATH)/imixcol.vhd \ + $(SRC_PATH)/forkaes.vhd \ + $(SRC_PATH)/forkaes_tb.vhd + +TB_MODULE = forkaes_tb + +WORKLIB = $(BUILD_DIR)/work-obj93.cf +WAVEFILE = wavefile.vcd + +all: verify + +$(BUILD_DIR): test_generator + mkdir -p $(BUILD_DIR) + cp test_vectors/Testinput.txt test_vectors/Testoutput.txt $(BUILD_DIR)/ + +$(WORKLIB): $(VHDL_SRCS) $(BUILD_DIR) + ghdl -a --ieee=synopsys -fexplicit --workdir=$(BUILD_DIR) $(VHDL_SRCS) + +elaborate: $(WORKLIB) $(BUILD_DIR) + ghdl -e --ieee=synopsys -fexplicit --workdir=$(BUILD_DIR) $(TB_MODULE) + +$(WAVEFILE): elaborate $(BUILD_DIR) + cd $(BUILD_DIR) && ghdl -r --ieee=synopsys -fexplicit $(TB_MODULE) --vcd=$(WAVEFILE) && cd .. + +analyse: $(WORKLIB) + +verify: $(WAVEFILE) + cd $(BUILD_DIR) && ../scripts/verify.sh && cd .. + +test_generator: + cd test_vectors && $(CC) case_generator.c -o case_generator.exe && ./case_generator.exe && cd .. + +clean: + rm -f $(WAVEFILE) $(WORKLIB) test_vectors/case_generator.exe test_vectors/Testinput.txt test_vectors/Testoutput.txt + rm -f test_vectors/case_generator.exe test_vectors/Testinput.txt test_vectors/Testoutput.txt + rm -rf $(BUILD_DIR) diff --git a/5_SC1_KC2_TC/scripts/analyze.sh b/5_SC1_KC2_TC/scripts/analyze.sh new file mode 100755 index 0000000..0016c92 --- /dev/null +++ b/5_SC1_KC2_TC/scripts/analyze.sh @@ -0,0 +1,22 @@ +#!/bin/tcsh +setenv SNPSLMD_LICENSE_FILE 27000@ielsrv01.epfl.ch + +setenv VCS_HOME /softs/synopsys/vcs-mx/N-2017.12-SP2-1 + +set path= ( $path $VCS_HOME/bin ) + +cp "../../test_vectors/Testinput.txt" "./Testinput.txt" +cp "../../test_vectors/Testoutput.txt" "./Testoutput.txt" + +vlogan -full64 /home/mballi/nangate45/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Verilog/NangateOpenCellLibrary.v + + +vlogan -full64 syn.v + +vhdlan -full64 ../../src/forkaes_tb.vhd + +vcs -full64 -debug -sdf typ:forkaes_tb/mut:syn.sdf forkaes_tb +neg_tchk +sdfverbose + +./simv -ucli -include ../scripts/saif.cmd + +#dve -full64 -toolexe simv diff --git a/5_SC1_KC2_TC/scripts/compile.tcl b/5_SC1_KC2_TC/scripts/compile.tcl new file mode 100644 index 0000000..05df24d --- /dev/null +++ b/5_SC1_KC2_TC/scripts/compile.tcl @@ -0,0 +1,46 @@ +sh rm -rf work/* +remove_design -all + +set basePath "../../src" +set commonfiles "${basePath}/xtime.vhd + ${basePath}/xxtime.vhd + ${basePath}/texpand.vhd + ${basePath}/circ_mult.vhd + ${basePath}/shiftrows.vhd + ${basePath}/enc.vhd + ${basePath}/sboxed.vhd + ${basePath}/sbox.vhd + ${basePath}/reg.vhd + ${basePath}/kreg.vhd + ${basePath}/mixcolumn.vhd + ${basePath}/mixcol.vhd + ${basePath}/mux128.vhd + ${basePath}/andmask.vhd + ${basePath}/keygen.vhd + ${basePath}/ishiftrows.vhd + ${basePath}/invmixcol.vhd + ${basePath}/imixcol.vhd + ${basePath}/forkaes.vhd" + + +define_design_lib work -path ./work +analyze -library work -format vhdl $commonfiles + +elaborate forkaes -architecture behav -library WORK +create_clock -name "ClkxCI" -period 100 -waveform { 0 50 } { ClkxCI } + +compile + +change_selection -name global -replace [get_timing_paths -delay_type max -nworst 1 -max_paths 1 -include_hierarchical_pins] + +uplevel #0 { report_timing -path full -delay max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group > timing.txt} + +uplevel #0 { report_area -hierarchy > area.txt} + +write -hierarchy -format verilog -output syn.v + +write_sdf syn.sdf + +write_file -hierarchy -output design_vision_session.ddc + +exit 0 diff --git a/5_SC1_KC2_TC/scripts/power.tcl b/5_SC1_KC2_TC/scripts/power.tcl new file mode 100644 index 0000000..8be4ca1 --- /dev/null +++ b/5_SC1_KC2_TC/scripts/power.tcl @@ -0,0 +1,11 @@ +read_file -format ddc {./design_vision_session.ddc} + +reset_switching_activity + +read_saif -verbose -input full-timing.saif -instance FORKAES_TB/MUT + +report_power > powercon_lp.txt + +report_power -hier > powerhier_lp.txt + +exit 0 diff --git a/5_SC1_KC2_TC/scripts/saif.cmd b/5_SC1_KC2_TC/scripts/saif.cmd new file mode 100644 index 0000000..a41316c --- /dev/null +++ b/5_SC1_KC2_TC/scripts/saif.cmd @@ -0,0 +1,7 @@ +power -gate_level on +power mut +power -enable +run 404200 ns +power -disable +power -report full-timing.saif 1e-09 mut +quit diff --git a/5_SC1_KC2_TC/scripts/verify.sh b/5_SC1_KC2_TC/scripts/verify.sh new file mode 100755 index 0000000..eea34df --- /dev/null +++ b/5_SC1_KC2_TC/scripts/verify.sh @@ -0,0 +1,6 @@ +#!/bin/bash +if diff Testoutput.txt tb_output.txt; then + echo "Simulation is successful" +else + echo "Simulated has failed" +fi diff --git a/5_SC1_KC2_TC/HDL/RTL/andmask.vhd b/5_SC1_KC2_TC/src/andmask.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/andmask.vhd rename to 5_SC1_KC2_TC/src/andmask.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/circ_mult.vhd b/5_SC1_KC2_TC/src/circ_mult.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/circ_mult.vhd rename to 5_SC1_KC2_TC/src/circ_mult.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/enc.vhd b/5_SC1_KC2_TC/src/enc.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/enc.vhd rename to 5_SC1_KC2_TC/src/enc.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/forkaes.vhd b/5_SC1_KC2_TC/src/forkaes.vhd similarity index 98% rename from 5_SC1_KC2_TC/HDL/RTL/forkaes.vhd rename to 5_SC1_KC2_TC/src/forkaes.vhd index 4ca7e04..80d5bb5 100644 --- a/5_SC1_KC2_TC/HDL/RTL/forkaes.vhd +++ b/5_SC1_KC2_TC/src/forkaes.vhd @@ -1,208 +1,210 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.all; entity forkaes is port( PTxDI : in std_logic_vector(127 downto 0); KeyxDI : in std_logic_vector(127 downto 0); TxDI : in std_logic_vector(63 downto 0); CTxDO : out std_logic_vector(127 downto 0); CTrdyxSO : out std_logic; InsxSI : in std_logic_vector(1 downto 0); ResetxRBI : in std_logic; ClkxCI : in std_logic ); end forkaes; architecture behav of forkaes is signal RoundxDP, RoundxDN: integer range 0 to 18; signal RowsxD, Rows1xD, MixedxD, Mixed1xD, BytesExD, BytesDxD, StxD, SPExD, SPDxD, PTxD: std_logic_vector(127 downto 0); signal SregxD, KregxD, TmpxD, CTxD : std_logic_vector(127 downto 0); signal SregxS, TmpxS, KregxS : std_logic_vector(1 downto 0); -- some enable signals signal t4xE, EncxE, DecxE, KeySchEncxE, KeySchDecxE : std_logic; -- the following are temporary signals signal t0, t1, t2, t3, t5, t6, t7, t12, t13, t14, t15: std_logic_vector(127 downto 0); signal TFullxD, RoundKeyEncxD, RoundKeyDecxD : std_logic_vector(127 downto 0); signal RconExD, RconDxD : std_logic_vector(7 downto 0); subtype Int8Type is integer range 0 to 255; type RconType is array (0 to 18) of Int8Type; --constant RconE : RconType := (0,1,2,4,8,16,32,64,128,27,54,108,216,171,77,154,47,0,0); --constant RconD : RconType := (0,54,27,128,64,32,16,8,4,2,1,0,0,0,0,0,0,0,0); --constant RconR : RconType := (0,54,27,128,64,32,108,216,171,77,154,47, 0, 0, 0, 0, 0, 0,0); constant RconE : RconType := (1,2,4,8,16,32,64,128,27,54,108,216,171,77,154,47,0,0,0); constant RconD : RconType := (54,27,128,64,32,16,8,4,2,1,0,0,0,0,0,0,0,0,0); constant RconR : RconType := (54,27,128,64,32,108,216,171,77,154,47, 0, 0, 0, 0, 0, 0,0,0); begin t0 <= PTxDI xor KeyxDI; texpand0 : entity texpand (ballif) port map(TxDI,TFullxD); t1 <= t0 xor TFullxD; imixcol0 : entity imixcol (ballif) port map(t1, t2); t3 <= TFullxD xor TmpxD; t5 <= t3 xor KregxD; sReg0: entity reg (ballif) port map(StxD, t5, t1, t2, ClkxCI, SregxS, SregxD); tmp0: entity reg (ballif) port map(MixedxD, TmpxD, PTxD, KeyxDI, ClkxCI, TmpxS, TmpxD); mux_kreg: entity mux128 (m128) port map(RoundKeyEncxD, RoundKeyDecxD, KeySchDecxE, t12); kReg0: entity kreg (ballif) port map(t12, ClkxCI, KregxD); -- State Func. g_sbox: for i in 0 to 15 generate i_sbox: entity sboxed (ed) port map (SregxD( ((i+1)*8)-1 downto i*8), BytesExD( ((i+1)*8)-1 downto i*8), BytesDxD( ((i+1)*8)-1 downto i*8)); end generate g_sbox; andmask2: entity andmask (ballif) port map(BytesExD, EncxE, SPExD); andmask3: entity andmask (ballif) port map(BytesDxD, DecxE, SPDxD); shiftrows0: entity shiftrows (permutation) port map(SPExD, RowsxD); ishiftrows0: entity ishiftrows (permutation) port map(SPDxD, Rows1xD); mixcol0: entity mixcol (ballif) port map(RowsxD, MixedxD); t6 <= Rows1xD xor TFullxD; andmask0: entity andmask (ballif) port map(KregxD, DecxE, t15); PTxD <= t15 xor t6; imixcol1: entity imixcol (ballif) port map(PTxD, Mixed1xD); t7 <= MixedxD xor TFullxD; CTxD <= t7 xor KregxD; mux0: entity mux128 (m128) port map(CTxD, Mixed1xD, DecxE, StxD); -- Key Func. --andmask4: entity andmask (ballif) port map(KregxD, KeySchEncxE, t9); --andmask5: entity andmask (ballif) port map(KregxD, KeySchDecxE, t10); mux_keygen0: entity mux128 (m128) port map(TmpxD, KeyxDI, KregxS(0), t14); mux_keygen1: entity mux128 (m128) port map(KregxD, t14, KregxS(1), t13); keygen0: entity keygen (ballif) port map (t13, RconExD, RconDxD, KeySchEncxE, KeySchDecxE, RoundKeyEncxD, RoundKeyDecxD); RconExD <= std_logic_vector(to_unsigned(RconE(RoundxDP),8)) when KeySchEncxE = '1' and InsxSI = "00" else std_logic_vector(to_unsigned(RconR(RoundxDP),8)) when KeySchEncxE = '1' and InsxSI = "10" else x"00" ; -- RconExD <= std_logic_vector(to_unsigned(RconE(RoundxDP),8)) when KeySchEncxE = '1' else x"00" ; RconDxD <= std_logic_vector(to_unsigned(RconD(RoundxDP),8)) when KeySchDecxE = '1' else x"00" ; mux1: entity mux128 (m128) port map(CTxD, PTxD, InsxSI(0), CTxDO); -- control block for all control signals process (ResetxRBI, RoundxDP, InsxSI) begin + TmpxS <= "01"; SregxS <= "00"; KregxS <= "01"; CTrdyxSO <= '0'; + -- power save mode below (not necessary for circuit correctness) RoundxDN <= RoundxDP; t4xE <= '0'; EncxE <= '0'; DecxE <= '0'; KeySchEncxE <= '0'; KeySchDecxE <= '0'; if ResetxRBI = '1' then if InsxSI = "00" then -- enc RoundxDN <= RoundxDP + 1; TmpxS <= "01"; SregxS <= "00"; KregxS <= "01"; EncxE <= '1'; DecxE <= '0'; KeySchEncxE <= '1'; KeySchDecxE <= '0'; t4xE <= '0'; CTrdyxSO <= '0'; case RoundxDP is when 0 => SregxS <= "10"; KregxS <= "11"; when 5 => TmpxS <= "00"; when 10 => CTrdyxSO <= '1'; when 11 => SregxS <= "01"; EncxE <= '0'; t4xE <= '1'; when 16 => CTrdyxSO <= '1'; when 17 => EncxE <= '0'; KeySchEncxE <= '0'; RoundxDN <= 17; when others => null; end case; elsif InsxSI = "01" then --dec RoundxDN <= RoundxDP + 1; TmpxS <= "01"; SregxS <= "00"; KregxS <= "01"; EncxE <= '0'; DecxE <= '1'; KeySchEncxE <= '0'; KeySchDecxE <= '1'; t4xE <= '0'; CTrdyxSO <= '0'; case RoundxDP is when 0 => SregxS <= "11"; KregxS <= "11"; when 5 => TmpxS <= "00"; when 10 => CTrdyxSO <= '1'; RoundxDN <= 17; when 17 => RoundxDN <= 17; when others => null; end case; elsif InsxSI = "10" then --rec0 RoundxDN <= RoundxDP + 1; TmpxS <= "01"; SregxS <= "00"; KregxS <= "01"; EncxE <= '0'; DecxE <= '1'; KeySchEncxE <= '0'; KeySchDecxE <= '1'; t4xE <= '0'; CTrdyxSO <= '0'; case RoundxDP is when 0 => TmpxS <= "11"; SregxS <= "11"; KregxS <= "11"; when 5 => TmpxS <= "10"; KregxS <= "10"; KeySchEncxE <= '1'; KeySchDecxE <= '0'; when 6 => SregxS <= "01"; --KregxS <= "00"; EncxE <= '0'; DecxE <= '0'; KeySchEncxE <= '1'; KeySchDecxE <= '0'; t4xE <= '1'; when 7| 8| 9 | 10 => --KregxS <= "00"; EncxE <= '1'; DecxE <= '0'; KeySchEncxE <= '1'; KeySchDecxE <= '0'; when 11 => EncxE <= '1'; DecxE <= '0'; KeySchEncxE <= '1'; KeySchDecxE <= '0'; CTrdyxSO <= '1'; RoundxDN <= 17; when 17 => RoundxDN <= 17; when others => null; end case; end if; end if; end process; process (ResetxRBI, ClkxCI) begin if ResetxRBI = '0' then RoundxDP <= 0; elsif ClkxCI'event and ClkxCI ='1' then RoundxDP <= RoundxDN; end if; end process; end architecture behav; diff --git a/5_SC1_KC2_TC/HDL/TBENCH/forkaes_tb.vhd b/5_SC1_KC2_TC/src/forkaes_tb.vhd similarity index 89% rename from 5_SC1_KC2_TC/HDL/TBENCH/forkaes_tb.vhd rename to 5_SC1_KC2_TC/src/forkaes_tb.vhd index b6ef10b..1dd1c88 100755 --- a/5_SC1_KC2_TC/HDL/TBENCH/forkaes_tb.vhd +++ b/5_SC1_KC2_TC/src/forkaes_tb.vhd @@ -1,120 +1,131 @@ library std; use std.textio.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; --use work.aes_pack.all; entity forkaes_tb is end forkaes_tb; architecture tb of forkaes_tb is constant clkphase: time:= 50 ns; constant resetactivetime: time:= 25 ns; file testinput, testoutput : TEXT; signal PTxD, KeyxD, CTxD : std_logic_vector (127 downto 0); signal TxD : std_logic_vector (63 downto 0); signal InsxS : std_logic_vector(1 downto 0); signal CTrdyxS : std_logic; signal ClkxC : std_logic; -- driving clock signal ResetxRB: std_logic; -- reset + signal cont_flag : boolean := true; component forkaes port( PTxDI : in std_logic_vector(127 downto 0); KeyxDI : in std_logic_vector(127 downto 0); TxDI : in std_logic_vector(63 downto 0); CTxDO : out std_logic_vector(127 downto 0); CTrdyxSO : out std_logic; InsxSI : in std_logic_vector(1 downto 0); ResetxRBI : in std_logic; ClkxCI : in std_logic ); end component; begin -- Instantiate the module under test (MUT) mut: forkaes port map ( PTxDI => PTxD, KeyxDI => KeyxD, TxDI => TxD, CTxDO => CTxD, CTrdyxSO => CTrdyxS, InsxSI => InsxS, ResetxRBI => ResetxRB, ClkxCI => ClkxC ); process begin - ClkxC <= '1'; wait for clkphase; - ClkxC <= '0'; wait for clkphase; + if cont_flag then + ClkxC <= '1'; + wait for clkphase; + ClkxC <= '0'; + wait for clkphase; + else + wait; + end if; end process; -- obtain stimulus and apply it to MUT ---------------------------------------------------------------------------- a : process variable INLine : line; variable tmp128 : std_logic_vector(127 downto 0); variable tmp2 : std_logic_vector(3 downto 0); variable tmp64 : std_logic_vector(63 downto 0); variable waitcycles : Integer; variable waitphase : time; begin + cont_flag <= true; file_open(testinput, "Testinput.txt", read_mode); - file_open(testoutput, "Testoutput2.txt", write_mode); + file_open(testoutput, "tb_output.txt", write_mode); ResetxRB <= '0'; PTxD <= (others => '0'); TxD <= (others => '0'); KeyxD <= (others => '0'); InsxS <= "00"; wait for resetactivetime; ResetxRB <= '1'; appli_loop : while not (endfile(testinput)) loop -- the structure of TB file should be: PT (hex) \n Key (hex) \n T(hex) \n Ins (bits) readline(testinput, INLine); hread(INLine, tmp128); PTxD <= tmp128; readline(testinput, INLine); hread(INLine, tmp128); KeyxD <= tmp128; readline(testinput, INLine); hread(INLine, tmp64); TxD <= tmp64; readline(testinput, INLine); hread(INLine, tmp2); InsxS <= tmp2(1 downto 0); if tmp2 = x"0" then wait for 2*10*clkphase; hwrite(INLine, CTxD); writeline(testoutput, INLine); wait for 2*6*clkphase; hwrite(INLine, CTxD); writeline(testoutput, INLine); wait for 2*clkphase - resetactivetime; elsif tmp2 = x"1" then wait for 2*10*clkphase; hwrite(INLine, CTxD); writeline(testoutput, INLine); wait for 2*clkphase - resetactivetime; elsif tmp2 = x"2" then wait for 2*11*clkphase; hwrite(INLine, CTxD); writeline(testoutput, INLine); wait for 2*clkphase - resetactivetime; else report "halted" severity error; end if; ResetxRB <= '0'; wait for resetactivetime; ResetxRB <= '1'; end loop appli_loop; wait until ClkxC'event and ClkxC = '1'; + file_close(testinput); + file_close(testoutput); + cont_flag <= false; wait; end process a; end tb; diff --git a/5_SC1_KC2_TC/HDL/RTL/imixcol.vhd b/5_SC1_KC2_TC/src/imixcol.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/imixcol.vhd rename to 5_SC1_KC2_TC/src/imixcol.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/invmixcol.vhd b/5_SC1_KC2_TC/src/invmixcol.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/invmixcol.vhd rename to 5_SC1_KC2_TC/src/invmixcol.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/ishiftrows.vhd b/5_SC1_KC2_TC/src/ishiftrows.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/ishiftrows.vhd rename to 5_SC1_KC2_TC/src/ishiftrows.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/keygen.vhd b/5_SC1_KC2_TC/src/keygen.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/keygen.vhd rename to 5_SC1_KC2_TC/src/keygen.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/kreg.vhd b/5_SC1_KC2_TC/src/kreg.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/kreg.vhd rename to 5_SC1_KC2_TC/src/kreg.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/mixcol.vhd b/5_SC1_KC2_TC/src/mixcol.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/mixcol.vhd rename to 5_SC1_KC2_TC/src/mixcol.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/mixcolumn.vhd b/5_SC1_KC2_TC/src/mixcolumn.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/mixcolumn.vhd rename to 5_SC1_KC2_TC/src/mixcolumn.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/mux128.vhd b/5_SC1_KC2_TC/src/mux128.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/mux128.vhd rename to 5_SC1_KC2_TC/src/mux128.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/reg.vhd b/5_SC1_KC2_TC/src/reg.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/reg.vhd rename to 5_SC1_KC2_TC/src/reg.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/sbox.vhd b/5_SC1_KC2_TC/src/sbox.vhd similarity index 99% rename from 5_SC1_KC2_TC/HDL/RTL/sbox.vhd rename to 5_SC1_KC2_TC/src/sbox.vhd index fe0d46c..14f6cb7 100755 --- a/5_SC1_KC2_TC/HDL/RTL/sbox.vhd +++ b/5_SC1_KC2_TC/src/sbox.vhd @@ -1,302 +1,302 @@ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use std.textio.all; use work.all; entity sbox is port ( InpxDI : in std_logic_vector(7 downto 0); OupxDO : out std_logic_vector(7 downto 0)); end entity sbox; architecture ed of sbox is signal PinxD,PoutxD: std_logic_vector( 255 downto 0); signal C1xD,C2xD,D1xD,D2xD: std_logic_vector(3 downto 0); signal P1xD,P2xD: std_logic_vector (15 downto 0); signal NAxD: std_logic_vector (7 downto 0); signal IxD: integer range 0 to 255; signal E1xD,F1xD: std_logic_vector (63 downto 0); signal G1xD,E2xD,F2xD,GF2xD : std_logic_vector(31 downto 0); signal H1xD,E3xD,F3xD,GF3xD,HF2xD,HGF3xD : std_logic_vector(15 downto 0); signal I1xD,E4xD,F4xD,GF4xD,HGF4xD,IF2xD,IGF3xD,IHGF4xD : std_logic_vector(7 downto 0); signal J1xD,E5xD,F5xD,GF5xD,HGF5xD,IHGF5xD,JF2xD,JGF3xD,JHGF4xD,JIHGF5xD : std_logic_vector(3 downto 0); signal K1xD,E6xD,F6xD,GF6xD,HGF6xD,IHGF6xD,JIHGF6xD,KF2xD,KGF3xD,KHGF4xD,KIHGF5xD,KJIHGF6xD : std_logic_vector(1 downto 0); signal L1xD,LF2xD,LGF3xD,LHGF4xD,LIHGF5xD,LJIHGF6xD : std_logic; subtype Int8Type is integer range 0 to 255; type Int8Array is array (0 to 255) of Int8Type; - constant SBOX : Int8Array := ( + constant SBOX_table : Int8Array := ( 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118, 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192, 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21, 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117, 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132, 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207, 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168, 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210, 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115, 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219, 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121, 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8, 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138, 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158, 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223, 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22 ); begin NAxD <= not InpxDI; a000: C1xD(0) <= NAxD(0) and NAxD(1) ; a001: C1xD(1) <= InpxDI(0) and NAxD(1) ; a002: C1xD(2) <= NAxD(0) and InpxDI(1) ; a003: C1xD(3) <= InpxDI(0) and InpxDI(1) ; x000: D1xD(0) <= NAxD(2) and NAxD(3) ; x001: D1xD(1) <= InpxDI(2) and NAxD(3) ; x002: D1xD(2) <= NAxD(2) and InpxDI(3) ; x003: D1xD(3) <= InpxDI(2) and InpxDI(3) ; y000: P1xD(0) <= C1xD(0) and D1xD(0); y001: P1xD(1) <= C1xD(1) and D1xD(0); y002: P1xD(2) <= C1xD(2) and D1xD(0); y003: P1xD(3) <= C1xD(3) and D1xD(0); y004: P1xD(4) <= C1xD(0) and D1xD(1); y005: P1xD(5) <= C1xD(1) and D1xD(1); y006: P1xD(6) <= C1xD(2) and D1xD(1); y007: P1xD(7) <= C1xD(3) and D1xD(1); y008: P1xD(8) <= C1xD(0) and D1xD(2); y009: P1xD(9) <= C1xD(1) and D1xD(2); y010: P1xD(10) <= C1xD(2) and D1xD(2); y011: P1xD(11) <= C1xD(3) and D1xD(2); y012: P1xD(12) <= C1xD(0) and D1xD(3); y013: P1xD(13) <= C1xD(1) and D1xD(3); y014: P1xD(14) <= C1xD(2) and D1xD(3); y015: P1xD(15) <= C1xD(3) and D1xD(3); b000: C2xD(0) <= NAxD(4) and NAxD(5) ; b001: C2xD(1) <= InpxDI(4) and NAxD(5) ; b002: C2xD(2) <= NAxD(4) and InpxDI(5) ; b003: C2xD(3) <= InpxDI(4) and InpxDI(5) ; w000: D2xD(0) <= NAxD(6) and NAxD(7) ; w001: D2xD(1) <= InpxDI(6) and NAxD(7) ; w002: D2xD(2) <= NAxD(6) and InpxDI(7) ; w003: D2xD(3) <= InpxDI(6) and InpxDI(7) ; z000: P2xD(0) <= C2xD(0) and D2xD(0); z001: P2xD(1) <= C2xD(1) and D2xD(0); z002: P2xD(2) <= C2xD(2) and D2xD(0); z003: P2xD(3) <= C2xD(3) and D2xD(0); z004: P2xD(4) <= C2xD(0) and D2xD(1); z005: P2xD(5) <= C2xD(1) and D2xD(1); z006: P2xD(6) <= C2xD(2) and D2xD(1); z007: P2xD(7) <= C2xD(3) and D2xD(1); z008: P2xD(8) <= C2xD(0) and D2xD(2); z009: P2xD(9) <= C2xD(1) and D2xD(2); z010: P2xD(10) <= C2xD(2) and D2xD(2); z011: P2xD(11) <= C2xD(3) and D2xD(2); z012: P2xD(12) <= C2xD(0) and D2xD(3); z013: P2xD(13) <= C2xD(1) and D2xD(3); z014: P2xD(14) <= C2xD(2) and D2xD(3); z015: P2xD(15) <= C2xD(3) and D2xD(3); i_loop : for i in 0 to 15 generate j_loop : for j in 0 to 15 generate PinxD((16*j + i)) <= P1xD(i) nand P2xD(j); end generate j_loop; end generate i_loop; ------ k_loop : for k in 0 to 255 generate -PoutxD(SBOX(k)) <= PinxD(k); +PoutxD(SBOX_table(k)) <= PinxD(k); end generate k_loop; ------ l_loop : for l in 0 to 63 generate E1xD(l) <= PoutxD(4*l + 1) and PoutxD(4*l + 3); F1xD(l) <= PoutxD(4*l + 2) and PoutxD(4*l + 3); end generate l_loop; m_loop : for m in 0 to 31 generate G1xD(m) <= PoutxD(8*m + 4) and PoutxD(8*m + 5); end generate m_loop; n_loop : for n in 0 to 15 generate H1xD(n) <= PoutxD(16*n + 8) and PoutxD(16*n + 9); end generate n_loop; o_loop : for o in 0 to 7 generate I1xD(o) <= PoutxD(32*o + 16) and PoutxD(32*o + 17); end generate o_loop; p_loop : for p in 0 to 3 generate J1xD(p) <= PoutxD(64*p + 32) and PoutxD(64*p + 33); end generate p_loop; q_loop : for q in 0 to 1 generate K1xD(q) <= PoutxD(128*q + 64) and PoutxD(128*q + 65); end generate q_loop; L1xD <= PoutxD(128) and PoutxD(129); r_loop : for r in 0 to 31 generate E2xD(r) <= E1xD(2*r) and E1xD (2*r+1); F2xD(r) <= F1xD(2*r) and F1xD (2*r+1); GF2xD(r) <= G1xD(r) and F1xD (2*r+1); end generate r_loop; s_loop : for s in 0 to 15 generate E3xD(s) <= E2xD(2*s) and E2xD (2*s+1); F3xD(s) <= F2xD(2*s) and F2xD (2*s+1); HF2xD(s) <= H1xD(s) and F1xD (4*s+2); GF3xD(s) <= GF2xD(2*s) and GF2xD(2*s+1); HGF3xD(s) <= HF2xD(s) and GF2xD(2*s+1); end generate s_loop; t_loop : for t in 0 to 7 generate E4xD(t) <= E3xD(2*t) and E3xD (2*t+1); F4xD(t) <= F3xD(2*t) and F3xD (2*t+1); IF2xD(t) <= I1xD(t) and F1xD(8*t+4); GF4xD(t) <= GF3xD(2*t) and GF3xD(2*t+1); HGF4xD(t) <= HGF3xD(2*t) and HGF3xD(2*t+1); IGF3xD(t) <= IF2xD(t) and GF2xD(4*t+2); IHGF4xD(t) <= IGF3xD(t) and HGF3xD(2*t+1); end generate t_loop; u_loop : for u in 0 to 3 generate E5xD(u) <= E4xD(2*u) and E4xD (2*u+1); F5xD(u) <= F4xD(2*u) and F4xD (2*u+1); JF2xD(u) <= J1xD(u) and F1xD(16*u+8); GF5xD(u) <= GF4xD(2*u) and GF4xD (2*u+1); HGF5xD(u) <= HGF4xD(2*u) and HGF4xD (2*u+1); JGF3xD(u) <= JF2xD(u) and GF2xD(8*u+4); JHGF4xD(u) <= JGF3xD(u) and HGF3xD(4*u+2); JIHGF5xD(u) <= JHGF4xD(u) and IHGF4xD(2*u+1); IHGF5xD(u) <= IHGF4xD(2*u) and IHGF4xD (2*u+1); end generate u_loop; v_loop : for v in 0 to 1 generate E6xD(v) <= E5xD(2*v) and E5xD (2*v+1); F6xD(v) <= F5xD(2*v) and F5xD (2*v+1); KF2xD(v) <= K1xD(v) and F1xD(32*v+16); GF6xD(v) <= GF5xD(2*v) and GF5xD (2*v+1); HGF6xD(v) <= HGF5xD(2*v) and HGF5xD (2*v+1); IHGF6xD(v) <= IHGF5xD(2*v) and IHGF5xD (2*v+1); JIHGF6xD(v) <= JIHGF5xD(2*v) and JIHGF5xD(2*v+1); KGF3xD(v) <= KF2xD(v) and GF2xD(16*v+8); KHGF4xD(v) <= KGF3xD(v) and HGF3xD(8*v+4); KIHGF5xD(v) <= KHGF4xD(v) and IHGF4xD(4*v+2); KJIHGF6xD(v) <= KIHGF5xD(v) and JIHGF5xD(2*v+1); end generate v_loop; OupxDO(0) <= E6xD(0) nand E6xD(1); OupxDO(1) <= F6xD(0) nand F6xD(1); OupxDO(2) <= GF6xD(0) nand GF6xD(1); OupxDO(3) <= HGF6xD(0) nand HGF6xD(1); OupxDO(4) <= IHGF6xD(0) nand IHGF6xD(1); OupxDO(5) <= JIHGF6xD(0) nand JIHGF6xD(1); OupxDO(6) <= KJIHGF6xD(0) nand KJIHGF6xD(1); LF2xD <= L1xD and F1xD(32); LGF3xD <= LF2xD and GF2xD(16); LHGF4xD <= LGF3xD and HGF3xD(8); LIHGF5xD <= LHGF4xD and IHGF4xD(4); LJIHGF6xD <= LIHGF5xD and JIHGF5xD(2); OupxDO(7)<= LJIHGF6xD nand KJIHGF6xD(1); end architecture ed; diff --git a/5_SC1_KC2_TC/HDL/RTL/sboxed.vhd b/5_SC1_KC2_TC/src/sboxed.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/sboxed.vhd rename to 5_SC1_KC2_TC/src/sboxed.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/shiftrows.vhd b/5_SC1_KC2_TC/src/shiftrows.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/shiftrows.vhd rename to 5_SC1_KC2_TC/src/shiftrows.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/texpand.vhd b/5_SC1_KC2_TC/src/texpand.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/texpand.vhd rename to 5_SC1_KC2_TC/src/texpand.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/xtime.vhd b/5_SC1_KC2_TC/src/xtime.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/xtime.vhd rename to 5_SC1_KC2_TC/src/xtime.vhd diff --git a/5_SC1_KC2_TC/HDL/RTL/xxtime.vhd b/5_SC1_KC2_TC/src/xxtime.vhd similarity index 100% rename from 5_SC1_KC2_TC/HDL/RTL/xxtime.vhd rename to 5_SC1_KC2_TC/src/xxtime.vhd diff --git a/5_SC1_KC2_TC/test_vectors/case_generator.c b/5_SC1_KC2_TC/test_vectors/case_generator.c new file mode 100644 index 0000000..240d2b3 --- /dev/null +++ b/5_SC1_KC2_TC/test_vectors/case_generator.c @@ -0,0 +1,457 @@ +#include +#include +#include + +unsigned char sbox[256] = +{ + 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, + 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, + 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15, + 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, + 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, + 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, + 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8, + 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, + 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, + 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, + 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, + 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, + 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, + 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, + 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, + 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 +}; + + +unsigned char isbox[256] = +{ + 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, + 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, + 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E, + 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25, + 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, + 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA, 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84, + 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06, + 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02, 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, + 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA, 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73, + 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E, + 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89, 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, + 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20, 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4, + 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F, + 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, + 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D + +}; + + +unsigned char rcon[18]={0x0,0x1,0x2,0x4,0x8,0x10,0x20,0x40,0x80,0x1B,0x36,0x6C,0xD8,0xAB,0x4D,0x9A,0x2F,0x5E}; + + +void rotate(unsigned char *in) { + unsigned char a,c; + a = in[0]; + for(c=0;c<3;c++) + in[c] = in[c + 1]; + in[3] = a; +} + +/* This is the core key expansion, which, given a 4-byte value, + * does some scrambling */ +void schedule_core(unsigned char *in, unsigned char i) { + char a; + /* Rotate the input 8 bits to the left */ + rotate(in); + /* Apply Rijndael's s-box on all 4 bytes */ + for(a = 0; a < 4; a++) + in[a] = sbox[in[a]]; + /* On just the first byte, add 2^i to the byte */ + in[0] ^= rcon[i]; +} + + +void expand_key(unsigned char *in) { + unsigned char t[4]; + /* c is 16 because the first sub-key is the user-supplied key */ + unsigned int c = 16; + unsigned char i = 1; + unsigned char a; + + /* We need 17 sets of sixteen bytes each for 128-bit mode */ + while(c < 272) { + /* Copy the temporary variable over from the last 4-byte + * block */ + + for(a = 0; a < 4; a++) + t[a] = in[a + c - 4]; + /* Every four blocks (of four bytes), + * do a complex calculation */ + if(c % 16 == 0) { + schedule_core(t,i); + i++; + } + for(a = 0; a < 4; a++) { + in[c] = in[c - 16] ^ t[a]; + c++; + } + } +} + +unsigned char gmul2( unsigned char c) + +{ +unsigned char b; + b = c & 0x80; + c <<= 1; + if(b == 0x80) { + c ^= 0x1b; + } + +return c; +} + + +unsigned char gmul4( unsigned char c) +{ +unsigned char b; + b = c & 0x80; + c <<= 1; + if(b == 0x80) { + c ^= 0x1b; + } + + b = c & 0x80; + c <<= 1; + if(b == 0x80) { + c ^= 0x1b; + } + +return c; +} + + + +void Mcol (unsigned char* CT) +{ + + +unsigned char y1,y2,y3,y4,q0,q1,q2,q3; +int i; + +for(i=0;i<16;i+=4) { + y1 = gmul2(CT[i+0]) ^ CT[i+2] ; + y2 = gmul2(CT[i+1]) ^ CT[i+3] ; + + y3 = gmul2(CT[i+2]) ^ CT[i+0] ; + y4 = gmul2(CT[i+3]) ^ CT[i+1] ; + + q0 = y1^y2^CT[i+1]; q1= y2^y3^CT[i+2]; q2 = y3^y4^CT[i+3]; q3= y4^y1^CT[i+0]; + CT[i+0]=q0; CT[i+1]=q1;CT[i+2]=q2;CT[i+3]=q3; + + +} + + +} + + +void IMcol (unsigned char* CT) { + unsigned char y0,y1,y2,y3,y4,q0,q1,q2,q3; + int i; + + for(i=0;i<16;i+=4) { + y3 = gmul4 (CT[i+0] ^ CT[i+2]) ^ CT[i+0]; y2 = gmul4(CT[i+1] ^ CT[i+3]) ^ CT[i+1] ; + y1 = gmul4 (CT[i+0] ^ CT[i+2]) ^ CT[i+2]; y0 = gmul4(CT[i+1] ^ CT[i+3]) ^ CT[i+3] ; + + CT[i+0]=y3; CT[i+1]=y2; CT[i+2]=y1; CT[i+3]=y0; + + y1 = gmul2(CT[i+0]) ^ CT[i+2] ; + y2 = gmul2(CT[i+1]) ^ CT[i+3] ; + + y3 = gmul2(CT[i+2]) ^ CT[i+0] ; + y4 = gmul2(CT[i+3]) ^ CT[i+1] ; + + q0 = y1^y2^CT[i+1]; q1= y2^y3^CT[i+2]; q2 = y3^y4^CT[i+3]; q3= y4^y1^CT[i+0]; + CT[i+0]=q0; CT[i+1]=q1;CT[i+2]=q2;CT[i+3]=q3; + } +} + + +void SRow (unsigned char* CT) { + unsigned char t1,t2; + t1 = CT[1]; CT[1]=CT[5]; CT[5]=CT[9]; CT[9]=CT[13];CT[13]=t1; + t1 = CT[2]; CT[2]=CT[10]; t2= CT[6]; CT[6]=CT[14]; CT[10]= t1; CT[14] = t2; + t1 = CT[15]; CT[15]=CT[11]; CT[11]=CT[7]; CT[7] = CT[3]; CT[3]=t1; +} + + +void ISRow (unsigned char* CT) { + unsigned char t1,t2; + t1 = CT[13]; CT[13]=CT[9]; CT[9]=CT[5]; CT[5]=CT[1];CT[1]=t1; + t1 = CT[2]; CT[2]=CT[10]; t2= CT[6]; CT[6]=CT[14]; CT[10]= t1; CT[14] = t2; + t1 = CT[3]; CT[3]=CT[7]; CT[7]=CT[11]; CT[11] = CT[15]; CT[15]=t1; +} + +void SByte (unsigned char* CT) { + int i; + for(i=0;i<16;i++) CT[i] = sbox[ CT[i] ]; +} + +void ISByte (unsigned char* CT) { + int i; + for(i=0;i<16;i++) CT[i] = isbox[ CT[i] ]; +} + +void show(unsigned char * CT) { + +} + +/* Comment out the following with above to easily remove show calls +void show(unsigned char* CT) { + int i; + for(i=0;i<16;i++){printf("%02x ",CT[i]); if (i%4==3) printf(" ");} + printf("\n"); +} +*/ + +void RFunc (unsigned char* CT) { + SByte(CT); + SRow(CT); + show(CT); + Mcol(CT); + show(CT); +} + +void IRFunc (unsigned char* CT) { + show(CT); + IMcol(CT); + show(CT); + ISRow(CT); + ISByte(CT); + show(CT); +} + + + + +void Fork_enc(unsigned char* Key,unsigned char* T, unsigned char* PT, unsigned char* CT, unsigned char* IT, unsigned char* DecKey) { + + int i,round; + + unsigned char RKey[272]; + + for(i=0;i<16;i++) RKey [i]=Key[i]; + expand_key(RKey); + for(i=0;i<16;i++) DecKey[i] = RKey[160+i]; + + //printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n"); + for(i=0;i<17;i++)show(RKey+16*i); + //printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n"); + + + for(i=0;i<16;i++)CT[i]=PT[i]; + + + for(round=0;round<=4;round++) { + for(i=0;i<16;i++) CT[i] ^= (RKey[i+round*16]^T[i]); + //show(CT); + RFunc(CT); + //show(CT); + //printf("=====\n"); + } + + //printf("================================================\n"); + + for(i=0;i<16;i++)IT[i]=CT[i]; + + for(round=5;round<=9;round++) { + for(i=0;i<16;i++) CT[i] ^= (RKey[i+round*16]^T[i]); + RFunc(CT); + //show(CT); + //printf("=====\n"); + } + + + for(i=0;i<16;i++) CT[i] ^= (RKey[i+10*16]^T[i]); //CT1 + //show(CT); + + //printf("================================================\n"); + + //printf("%02x %02x %02x \n", IT[0],T[0], RKey[176]); + + for(round=11;round<=15;round++) { + for(i=0;i<16;i++) IT[i] ^= (RKey[i+round*16]^T[i]); + //show(IT); + RFunc(IT); + //show(IT); + //printf("=====\n"); + } + + + for(i=0;i<16;i++) IT[i] ^= (RKey[i+16*16]^T[i]); //CT2 + show(IT); + //printf("================================================\n"); + +} + + +void Fork_dec0(unsigned char* Key,unsigned char* T, unsigned char* CT, unsigned char* PT ) { + + int i,round; + + unsigned char RKey[272]; + + for(i=0;i<16;i++) RKey [i]=Key[i]; + expand_key(RKey); + + + for(i=0;i<16;i++)PT[i]=CT[i]; + + + for(round=10;round>=1;round--){ + show(RKey + round*16); + for(i=0;i<16;i++) PT[i] ^= (RKey[i+round*16]^T[i]); + IRFunc(PT); + //printf("=====\n"); + } + show(RKey); + for(i=0;i<16;i++) PT[i] ^= (RKey[i+0*16]^T[i]); //PT + show(PT); +} + + +void Fork_rec0(unsigned char* Key,unsigned char* T, unsigned char* IT, unsigned char* CT ) { + + int i,round; + + unsigned char RKey[272]; + + for(i=0;i<16;i++) RKey [i]=Key[i]; + expand_key(RKey); + + + + for(i=0;i<16;i++)IT[i]=CT[i]; + + for(round=10;round>=6;round--) { + for(i=0;i<16;i++) IT[i] ^= (RKey[i+round*16]^T[i]); + show(RKey + round*16); + IRFunc(IT); + //printf("=====\n"); + } + for(i=0;i<16;i++) IT[i] ^= (RKey[i+5*16]^T[i]); + show(RKey + 5*16); + show(IT); + //printf("=====\n"); + for(round=11;round<=15;round++) { + for(i=0;i<16;i++) IT[i] ^= (RKey[i+round*16]^T[i]); + show(RKey + round*16); + RFunc(IT); + //printf("=====\n"); + } + for(i=0;i<16;i++) IT[i] ^= (RKey[i+round*16]^T[i]); + show(RKey + round*16); + show(IT); + //printf("=====\n"); +} + + +void save_enc(FILE *in, FILE* out, unsigned char* Key, unsigned char* Tweak, unsigned char* PT, unsigned char* CT, unsigned char* IT) { + int i; + for(i=0;i<16;i++) fprintf(in, "%02X", PT[i]); fprintf(in, "\n"); + for(i=0;i<16;i++) fprintf(in, "%02X", Key[i]); fprintf(in, "\n"); + for(i=0;i<8;i++) fprintf(in, "%02X", Tweak[i]); fprintf(in, "\n"); + fprintf(in, "%01X", 0); fprintf(in, "\n"); + for(i=0;i<16;i++) fprintf(out, "%02X", CT[i]); fprintf(out, "\n"); + for(i=0;i<16;i++) fprintf(out, "%02X", IT[i]); fprintf(out, "\n"); +} + +void save_dec(FILE *in, FILE* out, unsigned char* DecKey, unsigned char* Tweak, unsigned char* PT, unsigned char* CT) { + int i; + for(i=0;i<16;i++) fprintf(in, "%02X", CT[i]); fprintf(in, "\n"); + for(i=0;i<16;i++) fprintf(in, "%02X", DecKey[i]); fprintf(in, "\n"); + for(i=0;i<8;i++) fprintf(in, "%02X", Tweak[i]); fprintf(in, "\n"); + fprintf(in, "%01X", 1); fprintf(in, "\n"); + for(i=0;i<16;i++) fprintf(out, "%02X", PT[i]); fprintf(out, "\n"); +} + +void save_rec(FILE *in, FILE* out, unsigned char* DecKey, unsigned char* Tweak, unsigned char* IT, unsigned char* CT) { + int i; + for(i=0;i<16;i++) fprintf(in, "%02X", CT[i]); fprintf(in, "\n"); + for(i=0;i<16;i++) fprintf(in, "%02X", DecKey[i]); fprintf(in, "\n"); + for(i=0;i<8;i++) fprintf(in, "%02X", Tweak[i]); fprintf(in, "\n"); + fprintf(in, "%01X", 2); fprintf(in, "\n"); + for(i=0;i<16;i++) fprintf(out, "%02X", IT[i]); fprintf(out, "\n"); +} + +void tweak_expand(unsigned char* Tweak, unsigned char* T) { + int i; + for(i=0;i<16;i++) { + if(i%4==0) + T[i] = Tweak[i/4]; + else if(i%4==1) + T[i] = Tweak[i/4+4]; + else + T[i] = 0; + } +} + +void random_testcase_gen(unsigned char* Key, unsigned char* Tweak, unsigned char* T, unsigned char* PT, unsigned char* CT, unsigned char* IT, unsigned char* DecKey) { + int i; + for(i = 0; i < 16; i++) sprintf(Key + i, "%X", rand() % 16); + for(i = 0; i < 8; i++) sprintf(Tweak + i, "%X", rand() % 16); + for(i = 0; i < 16; i++) sprintf(PT + i, "%X", rand() % 16); + tweak_expand(Tweak, T); + Fork_enc(Key, T, PT, CT, IT, DecKey); +} + +void main() +{ + + FILE *in = fopen("Testinput.txt", "w"); + FILE *out = fopen("Testoutput.txt", "w"); + + int i,j; + + // unsigned char Key[16]={0x2b, 0x7e, 0x15, 0x16, 0x28 , 0xae , 0xd2 , 0xa6 , 0xab , 0xf7 , 0x15 , 0x88 , 0x09 , 0xcf , 0x4f , 0x3c}; + // unsigned char PT[16]= {0x32, 0x43, 0xf6, 0xa8, 0x88 , 0x5a , 0x30 , 0x8d , 0x31 , 0x31 , 0x98 , 0xa2 , 0xe0 , 0x37 , 0x07 , 0x34}; + + unsigned char Key[16]={0x84 , 0x81 , 0x85 , 0xdf , 0xa9 , 0x51 , 0xf1 , 0x1e , 0x13 , 0x97 , 0x24 , 0x8a , 0x6a , 0x69 , 0x8b , 0x17}; + unsigned char PT[16]= {0xad , 0x40 , 0xa8 , 0x96 , 0xb1 , 0xc7 , 0xea , 0xa0 , 0x52 , 0xb1 , 0xa7 , 0x0b , 0xd6 , 0x45 , 0xdb , 0x66}; + unsigned char CT0[16]= {0x77 , 0x6f , 0xd5 , 0x14 , 0xcf , 0xe2 , 0x89 , 0x9a , 0x06 , 0x5c , 0xcd , 0xa5 , 0x4c , 0x44 , 0xe5 , 0x65}; + unsigned char Tweak[8]={0x12,0x23,0x34,0x45,0x56,0x67,0x78,0x83}; + + unsigned char T[16], CT[16], IT[16], P0[16], P1[16], R[16], DecKey[16]; + + tweak_expand(Tweak, T); + + // for(i=0;i<16;i++) if(i%4<2) T[i]=Tweak[k++]; else T[i]=0; + + Fork_enc(Key,T,PT,CT,IT,DecKey); + save_enc(in, out, Key, Tweak, PT, CT, IT); + + Fork_dec0(Key,T,CT0,P0); + save_dec(in, out, DecKey, Tweak, P0, CT0); + + Fork_rec0(Key,T,IT,CT0); + save_rec(in, out, DecKey, Tweak, IT, CT0); + + + + for(j=0; j<100; j++) { + random_testcase_gen(Key, Tweak, T, PT, CT, IT, DecKey); + save_enc(in, out, Key, Tweak, PT, CT, IT); + + random_testcase_gen(Key, Tweak, T, PT, CT, IT, DecKey); + save_dec(in, out, DecKey, Tweak, PT, CT); + + random_testcase_gen(Key, Tweak, T, PT, CT, IT, DecKey); + save_rec(in, out, DecKey, Tweak, IT, CT); + + } + + fclose(in); + fclose(out); +} + +