diff --git a/1_SC1_KC1_TC/src/forkaes.vhd b/1_SC1_KC1_TC/src/forkaes.vhd index 50bce7c..53df591 100644 --- a/1_SC1_KC1_TC/src/forkaes.vhd +++ b/1_SC1_KC1_TC/src/forkaes.vhd @@ -1,201 +1,204 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.all; entity forkaes is port( PTxDI : in std_logic_vector(127 downto 0); KeyxDI : in std_logic_vector(127 downto 0); TxDI : in std_logic_vector(63 downto 0); CTxDO : out std_logic_vector(127 downto 0); CTrdyxSO : out std_logic; InsxSI : in std_logic_vector(1 downto 0); ResetxRBI : in std_logic; ClkxCI : in std_logic ); end forkaes; architecture behav of forkaes is signal RoundxDP, RoundxDN: integer range 0 to 18; signal RowsxD, Rows1xD, MixedxD, Mixed1xD, BytesExD, BytesDxD, StxD, SPExD, SPDxD, PTxD: std_logic_vector(127 downto 0); signal SregxD, KregxD, TmpxD, CTxD : std_logic_vector(127 downto 0); signal SregxS, KregxS, TmpxS : std_logic_vector(1 downto 0); -- some enable signals signal t4xE, EncxE, DecxE, KeySchEncxE, KeySchDecxE : std_logic; -- the following are temporary signals signal t0, t1, t2, t3, t4, t5, t6, t7, t11: std_logic_vector(127 downto 0); signal TFullxD, RoundKeyEncxD, RoundKeyDecxD : std_logic_vector(127 downto 0); signal RconExD, RconDxD : std_logic_vector(7 downto 0); subtype Int8Type is integer range 0 to 255; type RconType is array (0 to 18) of Int8Type; constant RconE : RconType := (0,1,2,4,8,16,32,64,128,27,54,108,216,171,77,154,47,0,0); constant RconD : RconType := (0,54,27,128,64,32,16,8,4,2,1,0,0,0,0,0,0,0,0); constant RconR : RconType := (0,54,27,128,64,32,108,216,171,77,154,47, 0, 0, 0, 0, 0, 0,0); begin t0 <= PTxDI xor KeyxDI; texpand0 : entity texpand (ballif) port map(TxDI,TFullxD); t1 <= t0 xor TFullxD; imixcol0 : entity imixcol (ballif) port map(t1, t2); t3 <= t11 xor TmpxD; andmask0: entity andmask (ballif) port map(RoundKeyEncxD, t4xE, t4); andmask1: entity andmask (ballif) port map(TFullxD, t4xE, t11); t5 <= t3 xor t4; sReg0: entity reg (ballif) port map(StxD, t5, t1, t2, ClkxCI, SregxS, SregxD); tmp0: entity reg (ballif) port map(MixedxD, TmpxD, PTxD, KeyxDI, ClkxCI, TmpxS, TmpxD); kReg0: entity reg (ballif) port map(RoundKeyEncxD, RoundKeyDecxD, KeyxDI, TmpxD, ClkxCI, KregxS, KregxD); -- State Func. g_sbox: for i in 0 to 15 generate i_sbox: entity sboxed (ed) port map (SregxD( ((i+1)*8)-1 downto i*8), BytesExD( ((i+1)*8)-1 downto i*8), BytesDxD( ((i+1)*8)-1 downto i*8)); end generate g_sbox; andmask2: entity andmask (ballif) port map(BytesExD, EncxE, SPExD); andmask3: entity andmask (ballif) port map(BytesDxD, DecxE, SPDxD); shiftrows0: entity shiftrows (permutation) port map(SPExD, RowsxD); ishiftrows0: entity ishiftrows (permutation) port map(SPDxD, Rows1xD); mixcol0: entity mixcol (ballif) port map(RowsxD, MixedxD); t6 <= Rows1xD xor TFullxD; PTxD <= RoundKeyDecxD xor t6; imixcol1: entity imixcol (ballif) port map(PTxD, Mixed1xD); t7 <= MixedxD xor TFullxD; CTxD <= t7 xor RoundKeyEncxD; mux0: entity mux128 (m128) port map(CTxD, Mixed1xD, DecxE, StxD); -- Key Func. --andmask4: entity andmask (ballif) port map(KregxD, KeySchEncxE, t9); --andmask5: entity andmask (ballif) port map(KregxD, KeySchDecxE, t10); keygen0: entity keygen (ballif) port map (KregxD, RconExD, RconDxD, KeySchEncxE, KeySchDecxE, RoundKeyEncxD, RoundKeyDecxD); RconExD <= std_logic_vector(to_unsigned(RconE(RoundxDP),8)) when KeySchEncxE = '1' and InsxSI = "00" else std_logic_vector(to_unsigned(RconR(RoundxDP),8)) when KeySchEncxE = '1' and InsxSI = "10" else x"00" ; -- RconExD <= std_logic_vector(to_unsigned(RconE(RoundxDP),8)) when KeySchEncxE = '1' else x"00" ; RconDxD <= std_logic_vector(to_unsigned(RconD(RoundxDP),8)) when KeySchDecxE = '1' else x"00" ; mux1: entity mux128 (m128) port map(CTxD, PTxD, InsxSI(0), CTxDO); -- control block for all control signals process (ResetxRBI, RoundxDP, InsxSI) begin + -- prevent latches + TmpxS <= "00"; SregxS <= "00"; KregxS <= "00"; CTrdyxSO <= '0'; + -- power save mode below (not necessary for circuit correctness) RoundxDN <= RoundxDP; t4xE <= '0'; EncxE <= '0'; DecxE <= '0'; KeySchEncxE <= '0'; KeySchDecxE <= '0'; if ResetxRBI = '1' then if InsxSI = "00" then -- enc RoundxDN <= RoundxDP + 1; TmpxS <= "01"; SregxS <= "00"; KregxS <= "00"; EncxE <= '1'; DecxE <= '0'; KeySchEncxE <= '1'; KeySchDecxE <= '0'; t4xE <= '0'; CTrdyxSO <= '0'; case RoundxDP is when 0 => SregxS <= "10"; KregxS <= "10"; when 5 => TmpxS <= "00"; when 10 => CTrdyxSO <= '1'; when 11 => SregxS <= "01"; EncxE <= '0'; t4xE <= '1'; when 16 => CTrdyxSO <= '1'; when 17 => EncxE <= '0'; KeySchEncxE <= '0'; RoundxDN <= 17; when others => null; end case; elsif InsxSI = "01" then --dec RoundxDN <= RoundxDP + 1; TmpxS <= "01"; SregxS <= "00"; KregxS <= "01"; EncxE <= '0'; DecxE <= '1'; KeySchEncxE <= '0'; KeySchDecxE <= '1'; t4xE <= '0'; CTrdyxSO <= '0'; case RoundxDP is when 0 => SregxS <= "11"; KregxS <= "10"; when 5 => TmpxS <= "00"; when 10 => CTrdyxSO <= '1'; RoundxDN <= 17; when 17 => RoundxDN <= 17; when others => null; end case; elsif InsxSI = "10" then --rec0 RoundxDN <= RoundxDP + 1; TmpxS <= "01"; SregxS <= "00"; KregxS <= "01"; EncxE <= '0'; DecxE <= '1'; KeySchEncxE <= '0'; KeySchDecxE <= '1'; t4xE <= '0'; CTrdyxSO <= '0'; case RoundxDP is when 0 => TmpxS <= "11"; SregxS <= "11"; KregxS <= "10"; when 5 => TmpxS <= "10"; KregxS <= "11"; when 6 => SregxS <= "01"; KregxS <= "00"; EncxE <= '0'; DecxE <= '0'; KeySchEncxE <= '1'; KeySchDecxE <= '0'; t4xE <= '1'; when 7| 8| 9 | 10 => KregxS <= "00"; EncxE <= '1'; DecxE <= '0'; KeySchEncxE <= '1'; KeySchDecxE <= '0'; when 11 => EncxE <= '1'; DecxE <= '0'; KeySchEncxE <= '1'; KeySchDecxE <= '0'; CTrdyxSO <= '1'; RoundxDN <= 17; when 17 => RoundxDN <= 17; when others => null; end case; end if; end if; end process; process (ResetxRBI, ClkxCI) begin if ResetxRBI = '0' then RoundxDP <= 0; elsif ClkxCI'event and ClkxCI ='1' then RoundxDP <= RoundxDN; end if; end process; end architecture behav;