Page Menu
Home
c4science
Search
Configure Global Search
Log In
Files
F123041269
drreg.vhd
No One
Temporary
Actions
Download File
Edit File
Delete File
View Transforms
Subscribe
Mute Notifications
Award Token
Subscribers
None
File Metadata
Details
File Info
Storage
Attached
Created
Thu, Jul 24, 10:37
Size
536 B
Mime Type
text/x-Algol68
Expires
Sat, Jul 26, 10:37 (2 d)
Engine
blob
Format
Raw Data
Handle
27619956
Attached To
R10499 Energy Analysis of Lightweight AEAD Circuit
drreg.vhd
View Options
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.all;
entity DRreg is
port (
RegxDN : in std_logic_vector (31 downto 0);
ClkxCI : in std_logic;
ResetxRBI : in std_logic;
RegxDP : out std_logic_vector (31 downto 0));
end entity DRreg;
architecture drr of DRreg is
begin
PROCESS(ClkxCI, ResetxRBI,RegxDN)
BEGIN
IF ClkxCI'event and ClkxCI ='1' then
if ResetxRBI='0' then
RegxDP <= (others=>'0') ;
else
RegxDP <= RegxDN;
end if;
END IF;
END PROCESS ;
end architecture drr;
Event Timeline
Log In to Comment