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<h1>Digital circuit sizing for an inverter chain (GP)</h1>
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<pre class="codeinput">
<span class="comment">% Boyd, Kim, Patil, and Horowitz, "Digital circuit optimization</span>
<span class="comment">% via geometric programming"</span>
<span class="comment">% Written for CVX by Almir Mutapcic 02/08/06</span>
<span class="comment">%</span>
<span class="comment">% We consider a chain of N inverters driving a load capacitance CL.</span>
<span class="comment">% The problem is to find optimal scale factors for the inverter</span>
<span class="comment">% that minimize the sum of them (area), while obeying constraints</span>
<span class="comment">% on the maximum delay through the circuit, and minimum and maximum</span>
<span class="comment">% limits on scale factors. There are no limits on the total power.</span>
<span class="comment">% (For more details about the inverter chain see sec. 2.1.11 in the paper.)</span>
<span class="comment">%</span>
<span class="comment">% minimize sum(x)</span>
<span class="comment">% s.t. T_j &lt;= Dmax for j an output gate</span>
<span class="comment">% T_j + d_i &lt;= T_i for j in FI(i)</span>
<span class="comment">% x_min &lt;= x &lt;= x_max</span>
<span class="comment">%</span>
<span class="comment">% where variables are x and T.</span>
<span class="comment">% Here we use data structures and digital circuit models from the</span>
<span class="comment">% referenced paper.</span>
<span class="comment">%********************************************************************</span>
<span class="comment">% problem data</span>
<span class="comment">%********************************************************************</span>
N = 8; <span class="comment">% number of inverters</span>
CL = 20; <span class="comment">% capacitance load</span>
Dmax = 20; <span class="comment">% maximum delay through the circuit</span>
x_min = 1; <span class="comment">% minimum scale factor</span>
x_max = 20; <span class="comment">% maximum scale factor</span>
<span class="comment">% circuit labeling convention:</span>
<span class="comment">% label primary input (input to the first inverter in the chain) with N+1</span>
<span class="comment">% label primary output (output of the last inverter in the chain) with N+2</span>
<span class="comment">% label inverters in the chain with 1,2,...,N based on their location</span>
<span class="comment">% primary input and primary output labels (start with N+1)</span>
primary_inputs = [N+1];
primary_outputs = [N+2];
M = N + length( primary_inputs ) + length( primary_outputs );
<span class="comment">% fan-in cell array for a straight chain of inverters</span>
FI{1} = [N+1]; <span class="comment">% fan-in of the first inverter is the primary input</span>
<span class="keyword">for</span> k = 2:N
FI{k} = [k-1]; <span class="comment">% fan-in of other inverters is the inverter feeding into them</span>
<span class="keyword">end</span>
FI{N+2} = [N]; <span class="comment">% fan-in of the primary output is the last inverter in the chain</span>
<span class="comment">% fan-out cell array</span>
<span class="comment">% (will be computed from the fan-in cell array, no need to modify)</span>
FO = cell(M,1);
<span class="keyword">for</span> gate = [1:N primary_outputs]
preds = FI{gate};
<span class="keyword">for</span> k = 1:length(preds)
FO{preds(k)}(end+1) = gate;
<span class="keyword">end</span>
<span class="keyword">end</span>
<span class="comment">% input and internal capacitance of gates and the driving resistance</span>
Cin_norm = ones(N,1);
Cint_norm = ones(N,1);
Rdrv_norm = ones(N,1);
<span class="comment">% place extra capacitance before the input of the 5th inverter</span>
Cin_norm(5) = 80;
<span class="comment">% primary output has Cin capacitance (but has no Cload)</span>
Cin_po = sparse(M,1);
Cin_po(primary_outputs) = CL;
<span class="comment">% primary input has Cload capacitance (but has no Cin)</span>
Cload_pi = sparse(M,1);
Cload_pi(primary_inputs) = 1;
<span class="comment">%********************************************************************</span>
<span class="comment">% optimization</span>
<span class="comment">%********************************************************************</span>
cvx_begin <span class="string">gp</span>
<span class="comment">% optimization variables</span>
variable <span class="string">x(N)</span> <span class="comment">% sizes</span>
variable <span class="string">T(N)</span> <span class="comment">% arrival times</span>
<span class="comment">% minimize the sum of scale factors subject to above constraints</span>
minimize( sum(x) )
subject <span class="string">to</span>
<span class="comment">% input capacitance is an affine function of sizes</span>
Cin = Cin_norm.*x;
Cint = Cint_norm.*x;
<span class="comment">% driving resistance is inversily proportional to sizes</span>
R = Rdrv_norm./x;
<span class="comment">% gate delay is the product of its driving resistance and load cap.</span>
Cload = cvx( zeros(N,1) );
<span class="keyword">for</span> gate = 1:N
<span class="keyword">if</span> ~ismember( FO{gate}, primary_outputs )
Cload(gate) = sum( Cin(FO{gate}) );
<span class="keyword">else</span>
Cload(gate) = Cin_po( FO{gate} );
<span class="keyword">end</span>
<span class="keyword">end</span>
<span class="comment">% delay</span>
D = 0.69*ones(N,1).*R.*( Cint + Cload );
<span class="comment">% create timing constraints</span>
<span class="keyword">for</span> gate = 1:N
<span class="keyword">if</span> ~ismember( FI{gate}, primary_inputs )
<span class="keyword">for</span> j = FI{gate}
<span class="comment">% enforce T_j + D_j &lt;= T_i over all gates j that drive i</span>
D(gate) + T(j) &lt;= T(gate);
<span class="keyword">end</span>
<span class="keyword">else</span>
<span class="comment">% enforce D_i &lt;= T_i for gates i connected to primary inputs</span>
D(gate) &lt;= T(gate);
<span class="keyword">end</span>
<span class="keyword">end</span>
<span class="comment">% circuit delay is the max of arrival times for output gates</span>
output_gates = [FI{primary_outputs}];
circuit_delay = max( T(output_gates) );
<span class="comment">% collect all the constraints</span>
circuit_delay &lt;= Dmax;
x_min &lt;= x &lt;= x_max;
cvx_end
<span class="comment">% message about extra capacitance and result display</span>
disp(<span class="string">' '</span>)
disp([<span class="string">'Note: there is an extra capacitance between the 4th and 5th inverter'</span><span class="keyword">...</span>
<span class="string">' in the chain.'</span>])
fprintf(1,<span class="string">'\nOptimal scale factors are: \n'</span>), x
<span class="comment">% plot scale factors and maximum delay for inverter i</span>
close <span class="string">all</span>;
subplot(2,1,1); plot([1:N],T,<span class="string">'g--'</span>,[1:N],T,<span class="string">'bo'</span>);
ylabel(<span class="string">'maximum delay T'</span>)
subplot(2,1,2); stem([1:N],x);
ylabel(<span class="string">'scale factor x'</span>)
xlabel(<span class="string">'inverter stage'</span>)
</pre>
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<pre class="codeoutput">
Successive approximation method to be employed.
For improved efficiency, SDPT3 is solving the dual problem.
SDPT3 will be called several times to refine the solution.
Original size: 154 variables, 69 equality constraints
38 exponentials add 304 variables, 190 equality constraints
-----------------------------------------------------------------
Cones | Errors |
Mov/Act | Centering Exp cone Poly cone | Status
--------+---------------------------------+---------
30/ 30 | 3.446e+00 6.441e-01 0.000e+00 | Unbounded
38/ 38 | 5.254e+00 1.528e+00 0.000e+00 | Solved
37/ 37 | 8.561e-01 5.489e-02 0.000e+00 | Solved
33/ 36 | 5.194e-02 1.829e-04 0.000e+00 | Solved
12/ 26 | 4.425e-03 1.328e-06 0.000e+00 | Solved
0/ 3 | 4.428e-04 1.214e-08 0.000e+00 | Solved
-----------------------------------------------------------------
Status: Solved
Optimal value (cvx_optval): +32.2496
Note: there is an extra capacitance between the 4th and 5th inverter in the chain.
Optimal scale factors are:
x =
3.0461
2.6553
4.3323
12.4395
1.0000
1.3185
2.2358
5.2220
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