\begin{example}[Implementation of AD and DA Converters]\label{ex:qt:physAD}
Analog-to-digital conversion is a process that lives at the interface between the physical world of electrical signals and the abstract world of numeric processing; it is carried out by specialized hardware devices that first measure the input signal's instantaneous value and then encode this value into a binary representation suitable for use on a general-purpose processors. Although a full description of the electronic circuitry used in ADCs and DACs is beyond the scope of this book, in this section we will examine the fundamental principles at work in these devices.
\itempar{The op-amp.} The fundamental component at the heart of an ADC is the operational amplifier, or \textit{op-amp}, whose symbolic representation is shown in Figure~\ref{fig:qt:opamp}. An op-amp, powered by a balanced power supply $(-V_{cc}, +V_{cc})$, is a differential amplifier whose output voltage is proportional to the difference between the voltages at the two inputs:
\[
v_0= G(v_+- v_-).
\]
The ideal op-amp has the following characteristics:
\begin{itemize}
\item the input and output impedance are infinite; as a consequence, op-amp inputs draw no current which is ideal if we need to measure a voltage source without affecting its value.
\item the gain is infinite, which means the op-amp will saturate to $\pm V_{cc}$ as soon as the voltage difference between the inputs is nonzero.
\end{itemize}
These properties are exploited in two of the classic configurations for the device, shown in Figure~\ref{fig:qt:comp_follower}:
\begin{enumerate}
\item to build a \textit{comparator} the op-amp is used in open-loop, with the inverting input connected to a reference voltage $V_T$; if the non-inverting input is connected to a voltage larger than $V_T$, then the output will saturate to the maximum possible voltage $V_{cc}$ whereas if $v_+ < V_T$, the output will drop to $-V{cc}$.
\item to build a \textit{voltage buffer}, the op-amp is used in closed loop, with the output fed back to the non-inverting input; if a source at $v$ Volts is now applied to the inverting input, the output will instantly adjust to $v_o = v$. To understand why, assume by contradiction that $v_o > v$; since $v_o = v$ via the feedback, $v_+- v_- < 0$ and the infinite gain would immediately drive the output down. Similarly, if it were $v_o < v$, the output would be immediately driven up, and so that the only stability point is $v_o = v$. The buffer function of the configuration derives its name from the infinite input impedance, which ensures that no current is drawn from the source applied to $v_+$; the load connected to the output will be driven at a voltage $v$ solely by the op-amp.
\end{enumerate}
\itempar{A sample-and-hold circuit.} These two properties are put to use in the sample-and-hold circuit shown in Figure~\ref{fig:qt:sampler}. The field-effect transistor {\em T1} acts as a solid-state switch, driven by a train of pulses $k(t)$ generated by a very stable crystal oscillator. The pulses arrive $F_s$ times per second and they cause {\em T1} to close briefly so that the capacitor {\em C1} is allowed to charge to the instantaneous value of the input voltage $x_c(nT_s)$; note that the current necessary to charge the capacitor is provided by the op-amp and not by the input, thanks to the buffer configuration of the former. The FET then opens immediately and the capacitor remains charged to $x_c(nT_s)$ over the time interval $\bigl[nT_s, (n+1)T_s \bigr]$; the capacitor therefore acts as memory element for the input signal's voltage across sampling instants and a second op-amp buffer isolates it from the quantization circuitry to follow.
\itempar{A simple flash quantizer.} Figure~\ref{fig:qt:twobitq} shows how a simple two-bit quantizer can be realized using three op-amps and some solid-state logic gates. The structure is called a {\em flash} (or {\em parallel}) quantizer since the input value is simultaneously compared to all of the quantization thresholds $i_k$. These are obtained via a voltage divider
realized by the cascade of equally-valued resistors, as shown on the left of the circuit. In this simple example, the signal
is quantized over the $[-V_0, V_0]$ interval with $2$~bits per sample and therefore four voltage levels are necessary. Using the notation of Section~\ref{sec:qt:scalarq} we have
\[
i_k =-V_0+(k/2)V_0, \quad k =0, 1, 2, 3, 4.
\]
The internal boundary voltages are connected as reference levels to a set of comparators; all the op-amps for which the reference voltage is less than the input voltage will saturate to a high output level and the logic network of XOR gates and diodes will convert the comparators' outputs into a two-digit binary value. Flash quantizers are extremely fast, which allows for use with high sampling frequencies. Unfortunately, the number of electronic components grows exponentially with the number of output bits and so the achievable resolution is small, on the order of 8 bits per sample.
Quantization is a key topic both in analog-to-digital conversion and in signal compression, but an often overlooked topic in standard texts. The book by A.\ Gersho and R.\ M.\ Gray, \textit{Vector Quantization and Signal Compression\/} (Springer, 1991) provides a good discussion of the subject. An excellent overview of quantization is given in R.\ M.\ Gray and D.\ L.\ Neuhof's article ``Quantization'', in \textit{IEEE Transactions on Information Theory\/} (October 1998).