library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.all;

entity keygen is
  port (
     KeyxDI      : in  std_logic_vector(127 downto 0);
     RconExDI     : in  std_logic_vector(7 downto 0); 
     RconDxDI     : in  std_logic_vector(7 downto 0); 
     EncxEI:        in std_logic;
     DecxEI:        in std_logic;
     RoundKeyEncxDO : out std_logic_vector(127 downto 0);
     RoundKeyDecxDO : out std_logic_vector(127 downto 0)
  );

end keygen;

architecture ballif of keygen is
  signal ExD, DxD   : std_logic_vector(127 downto 0); 

  signal RotWordxD, RotWord1xD : std_logic_vector(31 downto 0);
  signal SubWordxD, SubWord1xD: std_logic_vector(31 downto 0);
  signal TempxD,Temp1xD    : std_logic_vector(31 downto 0);
 
  signal RExD,RDxD: std_logic_vector(127 downto 0); 

  signal M0xD,M1xD,M2xD,M3xD : std_logic_vector(31 downto 0);
  signal N0xD,N1xD,N2xD,N3xD : std_logic_vector(31 downto 0);
  signal M23xD   : std_logic_vector(31 downto 0);

begin
 

   
--------------------------------------------------------------------
andmask0: entity andmask (ballif) port map (KeyxDI, EncxEI, RExD);
andmask1: entity andmask (ballif) port map (KeyxDI, DecxEI, RDxD);


--------------------------------------------------------------------
N0xD<= RExD(127 downto 96); 
N1xD<= RExD(95 downto 64);
N2xD<= RExD(63 downto 32);
N3xD<= RExD(31 downto 0);

RotWordxD <= N3xD(23 downto 0) & N3xD(31 downto 24);	
  
	g_sbox: for i in 0 to 3 generate
		i_sbox: entity sbox (ballif) port map (RotWordxD(8*i+7 downto i*8), SubWordxD(8*i+7 downto i*8));
	end generate g_sbox;

 
   
   TempxD(31 downto 24) <=RconExDI xor SubWordxD(31 downto 24);

   TempxD(23 downto 0) <=  SubWordxD(23 downto 0);



ExD(127 downto 96) <= N0xD xor TempxD;

ExD(95 downto 64) <= ExD(127 downto 96) xor N1xD;

ExD(63 downto 32) <= ExD(95 downto 64) xor N2xD;

ExD(31 downto 0) <= ExD(63 downto 32) xor N3xD;

--------------------------------------------------------------------

M0xD<= RDxD(127 downto 96); 
M1xD<= RDxD(95 downto 64);
M2xD<= RDxD(63 downto 32);
M3xD<= RDxD(31 downto 0);


M23xD <= M2xD xor M3xD;



RotWord1xD <= M23xD(23 downto 0) & M23xD(31 downto 24);	
  
	h_sbox: for i in 0 to 3 generate
		i_sbox2: entity sbox (ballif) port map (RotWord1xD(8*i+7 downto i*8), SubWord1xD(8*i+7 downto i*8));
	end generate h_sbox;

 
   
   Temp1xD(31 downto 24) <=RconDxDI xor SubWord1xD(31 downto 24);

   Temp1xD(23 downto 0) <=  SubWord1xD(23 downto 0);

DxD(127 downto 96) <= M0xD xor Temp1xD;

DxD(95 downto 64) <= M0xD xor M1xD;

DxD(63 downto 32) <= M1xD xor M2xD;

DxD(31 downto 0) <= M23xD;

RoundKeyEncxDO <= ExD;
RoundKeyDecxDO <= DxD;
         
end architecture ballif;