library ieee;
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
use std.textio.all;
use work.all;

entity reg is 
port (
D0xDI : in std_logic_vector (127 downto 0);
D1xDI : in std_logic_vector (127 downto 0);
D2xDI : in std_logic_vector (127 downto 0);
D3xDI : in std_logic_vector (127 downto 0);
ClkxCI : in std_logic;
En : in std_logic;
SelxSI : in std_logic_vector(1 downto 0);

StatexDP : out std_logic_vector (127 downto 0));
end entity reg;


architecture ballif of reg is

begin


       

p_clk: process (ClkxCI)
         begin
	if ClkxCI'event and ClkxCI ='1' and En = '0' then
		if SelxSI = "00" then
			StatexDP <= D0xDI;
		elsif SelxSI = "01" then 
			StatexDP <= D1xDI;
		elsif SelxSI = "10" then 
			StatexDP <= D2xDI;
		elsif SelxSI = "11" then 
			StatexDP <= D3xDI;
		end if;
	end if;
          
end process p_clk;

end architecture ballif;