library ieee;
use ieee.std_logic_1164.all;

entity xtime is
  
  port (
    InpxDI : in  std_logic_vector(7 downto 0);
    OupxDO : out std_logic_vector(7 downto 0)
    );

end xtime;


architecture structural of xtime is
  signal Y07xD,Y27xD,Y37xD : std_logic;

begin

  Y07xD <= InpxDI(7) xor InpxDI(0);
  Y27xD <= InpxDI(7) xor InpxDI(2);
  Y37xD <= InpxDI(7) xor InpxDI(3);


  OupxDO <= InpxDI(6 downto 4) & Y37xD &  Y27xD & InpxDI(1) & Y07xD & InpxDI(7);
end structural;