sh rm -rf work/*
remove_design -all

set basePath "../../src"
set commonfiles    "${basePath}/xtime.vhd
					${basePath}/xxtime.vhd
					${basePath}/clockgater.vhd
					${basePath}/circ_mult.vhd
					${basePath}/texpand.vhd
					${basePath}/shiftrows.vhd
					${basePath}/enc.vhd
					${basePath}/decoder.vhd
					${basePath}/sbox.vhd
					${basePath}/isbox.vhd
					${basePath}/reg.vhd
					${basePath}/mixcolumn.vhd
					${basePath}/mixcol.vhd
					${basePath}/mux128.vhd
					${basePath}/andmask.vhd
					${basePath}/keygen.vhd
					${basePath}/ishiftrows.vhd
					${basePath}/invmixcol.vhd
					${basePath}/imixcol.vhd
					${basePath}/controller.vhd
					${basePath}/forkaes.vhd"

                    
define_design_lib work -path ./work
analyze -library work -format vhdl $commonfiles

elaborate forkaes -architecture behav -library WORK
create_clock -name "ClkxCI" -period 100 -waveform { 0 50  }  { ClkxCI  }

compile

change_selection -name global -replace [get_timing_paths -delay_type max -nworst 1 -max_paths 1 -include_hierarchical_pins]

uplevel #0 { report_timing -path full -delay max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group > timing.txt}

uplevel #0 { report_area -hierarchy > area.txt}
 
write -hierarchy -format verilog -output syn.v 

write_sdf syn.sdf

write_file -hierarchy -output design_vision_session.ddc

exit 0