library ieee;
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
use std.textio.all;
use work.all;


entity andmask is
port ( InpxDI : in  std_logic_vector(127 downto 0);
       ExSI : in  std_logic;
       OupxDO  : out std_logic_vector(127 downto 0));
end entity andmask;



architecture ballif of andmask is 

begin

	a2: for i in 0 to 127 generate 
		OupxDO(i) <= InpxDI(i) and ExSI;
	end generate a2;

end architecture ballif;