library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.all;
     

entity forkaes is
  port(
        PTxDI     : in  std_logic_vector(127 downto 0);
        KeyxDI    : in  std_logic_vector(127 downto 0);
		TxDI    : in  std_logic_vector(63 downto 0);
        CTxDO    : out std_logic_vector(127 downto 0);
        CTrdyxSO	: out std_logic;
        InsxSI     : in  std_logic_vector(1 downto 0);
        ResetxRBI : in  std_logic;
        ClkxCI    : in  std_logic
      );

end forkaes;


architecture behav of forkaes is

 
	signal RowsxD, Rows1xD, MixedxD, Mixed1xD, BytesExD, BytesDxD, SPExD, SPDxD, PTxD: std_logic_vector(127 downto 0);
	signal SregxD, KregxD, CTxD : std_logic_vector(127 downto 0);
	signal KregxS : std_logic_vector(1 downto 0);
	signal SregxS : std_logic_vector(2 downto 0);
	-- clock signals
	signal Sreg_en, Kreg_en: std_logic;

	-- some enable signals
	signal t4xE, EncxE, DecxE, KeySchEncxE, KeySchDecxE: std_logic;
	
	-- the following are temporary signals
	signal t0, t1, t2, t3, t4, t5, t6, t7, t11: std_logic_vector(127 downto 0);
	signal TFullxD, RoundKeyEncxD, RoundKeyDecxD : std_logic_vector(127 downto 0);

	signal RconExD, RconDxD    : std_logic_vector(7 downto 0);


	constant zero128 : std_logic_vector(127 downto 0) := (others => '0');
  
begin
	
	t0 <= PTxDI xor KeyxDI;
	texpand0 : entity texpand (ballif) port map(TxDI,TFullxD);
	t1 <= t0 xor TFullxD;
	imixcol0 : entity imixcol (ballif) port map(t1, t2);
	
	
	andmask1: entity andmask (ballif) port map(SregxD, t4xE, t3);
	t11 <= TFullxD xor t3;
	andmask0: entity andmask (ballif) port map(RoundKeyEncxD, t4xE, t4);
	t5 <= t11 xor t4;
	
	-- tmp0:   entity reg (ballif) port map(MixedxD, zero128, PTxD, KeyxDI, TmpxC, TmpxS, TmpxD);
	sReg0: entity sreg (ballif) port map(CTxD, PTxD, Mixed1xD, RowsxD, t1, t2, t5, zero128, ClkxCI, Sreg_en, SregxS, SregxD);
	kReg0:  entity reg (ballif) port map(RoundKeyEncxD, RoundKeyDecxD,  KeyxDI, zero128, ClkxCI, Kreg_en, KregxS, KregxD);
	-- tReg0:  entity Treg (ballif) port map(TxDI, TregxC, TFullxD);
	
	-- State Func.
	g_sbox: for i in 0 to 15 generate 
		i_sbox: entity sboxed (ed)
		port map (SregxD( ((i+1)*8)-1 downto i*8), BytesExD( ((i+1)*8)-1 downto i*8), BytesDxD( ((i+1)*8)-1 downto i*8));
	end generate g_sbox;

	andmask2: entity andmask (ballif) port map(BytesExD, EncxE, SPExD);
	andmask3: entity andmask (ballif) port map(BytesDxD, DecxE, SPDxD);
	
	shiftrows0: entity shiftrows (permutation) port map(SPExD, RowsxD);
	ishiftrows0: entity ishiftrows (permutation) port map(SPDxD, Rows1xD);
	
	mixcol0: entity mixcol (ballif) port map(RowsxD, MixedxD);
	t6 <= Rows1xD xor TFullxD;
	PTxD <= RoundKeyDecxD xor t6;
	imixcol1: entity imixcol (ballif) port map(PTxD, Mixed1xD);
	
	t7 <= MixedxD xor TFullxD;
	CTxD <= t7 xor RoundKeyEncxD;
	
	keygen0: entity keygen (ballif) port map (KregxD, RconExD, RconDxD, KeySchEncxE, KeySchDecxE, RoundKeyEncxD, RoundKeyDecxD);
	mux1: entity mux128 (m128) port map(CTxD, PTxD, InsxSI(0), CTxDO);

	controller0 : entity controller (ballif) port map(InsxSI, ResetxRBI, ClkxCI, SregxS, KregxS, EncxE, DecxE, KeySchEncxE, KeySchDecxE, t4xE, CTrdyxSO, RconExD, RconDxD, Sreg_en, Kreg_en);
	
end architecture behav;