library ieee;
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
use std.textio.all;
use work.all;

entity sreg is 
port (
D0xDI : in std_logic_vector (127 downto 0);
D1xDI : in std_logic_vector (127 downto 0);
D2xDI : in std_logic_vector (127 downto 0);
D3xDI : in std_logic_vector (127 downto 0);
D4xDI : in std_logic_vector (127 downto 0);
D5xDI : in std_logic_vector (127 downto 0);
D6xDI : in std_logic_vector (127 downto 0);
D7xDI : in std_logic_vector (127 downto 0);
ClkxCI : in std_logic;
En	: in std_logic;
SelxSI : in std_logic_vector(2 downto 0);

StatexDP : out std_logic_vector (127 downto 0));
end entity sreg;


architecture ballif of sreg is

begin


       

p_clk: process (ClkxCI)
         begin

	if ClkxCI'event and ClkxCI ='1' and En='0' then
		if SelxSI = "000" then
			StatexDP <= D0xDI;
		elsif SelxSI = "001" then 
			StatexDP <= D1xDI;
		elsif SelxSI = "010" then 
			StatexDP <= D2xDI;
		elsif SelxSI = "011" then 
			StatexDP <= D3xDI;
		elsif SelxSI = "100" then 
			StatexDP <= D4xDI;
		elsif SelxSI = "101" then 
			StatexDP <= D5xDI;
		elsif SelxSI = "110" then 
			StatexDP <= D6xDI;
		elsif SelxSI = "111" then 
			StatexDP <= D7xDI;
		end if;
	end if;
          
end process p_clk;

end architecture ballif;