library ieee;
use ieee.std_logic_1164.all;

entity xxtime is
  
  port (
    InpxDI : in  std_logic_vector(7 downto 0);
    OupxDO : out std_logic_vector(7 downto 0)
    );

end xxtime;


architecture structural of xxtime is
signal Y67xD,Y07xD,Y267xD,Y16xD,Y37xD : std_logic;

begin

  Y67xD <= InpxDI(7) xor InpxDI(6);
  Y07xD <= InpxDI(7) xor InpxDI(0);
  Y16xD <= InpxDI(1) xor InpxDI(6);
  Y267xD <= InpxDI(2) xor Y67xD ;
  Y37xD <= InpxDI(7) xor InpxDI(3);


  OupxDO <= InpxDI(5 downto 4) & Y37xD &  Y267xD & Y16xD &   Y07xD & Y67xD & InpxDI(6);
end structural;