--- MC used by SATOH


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.all;



entity circ_mult is 
port ( InpxDI : in std_logic_vector (31 downto 0);
       OupxDO : out std_logic_vector (31 downto 0)
       );
       
end entity circ_mult;

architecture cm of circ_mult is
  
  signal A0xD,A1xD,A2xD,A3xD, X0xD,X1xD,X2xD,X3xD, Y0xD,Y1xD,Y2xD,Y3xD : std_logic_vector (7 downto 0);
  signal H0xD,H1xD,H2xD,H3xD, Z0xD,Z1xD,Z2xD,Z3xD, G0xD,G1xD,G2xD,G3xD , X02xD,X13xD,F02xD,F13xD: std_logic_vector (7 downto 0);
  signal GxD, HxD : std_logic_vector (31 downto 0);
begin 
  
  
A0xD <= InpxDI(31 downto 24);
A1xD <= InpxDI(23 downto 16);
A2xD <= InpxDI(15 downto 8);
A3xD <= InpxDI(7 downto 0);  



X02xD <= A2xD xor A0xD;
X13xD <= A1xD xor A3xD;

m1: entity xxtime (structural) port map (X02xD,F02xD);
m2: entity xxtime (structural) port map (X13xD,F13xD);

 
G0xD <= F02xD xor A0xD;
G1xD <= F13xD xor A1xD;
 
G2xD <= F02xD xor A2xD;
G3xD <= F13xD xor A3xD;

 


 

OupxDO <= G0xD & G1xD & G2xD & G3xD ;



 
end architecture cm;