--- MC used by SATOH


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.all;



entity invmixcol is 
port ( InpxDI : in std_logic_vector (31 downto 0);
       OupxDO : out std_logic_vector (31 downto 0)
       );
       
end entity invmixcol;

architecture ballif of invmixcol is
  
  signal A0xD,A1xD,A2xD,A3xD, X0xD,X1xD,X2xD,X3xD, Y0xD,Y1xD,Y2xD,Y3xD : std_logic_vector (7 downto 0);
  signal B0xD,B1xD,Q0xD,Q1xD, Z0xD,Z1xD,Z2xD,Z3xD, I0xD,I1xD,I2xD,I3xD, R0xD,R1xD,G0xD,G1xD,SxD,GxD : std_logic_vector (7 downto 0);

begin 
  
  
A0xD <= InpxDI(31 downto 24);
A1xD <= InpxDI(23 downto 16);
A2xD <= InpxDI(15 downto 8);
A3xD <= InpxDI(7 downto 0);  



X3xD <= A3xD xor A0xD;
X2xD <= A2xD xor A3xD;
X1xD <= A1xD xor A2xD;
X0xD <= A0xD xor A1xD;

xt1: entity xtime (structural) port map (X3xD,Y3xD);
xt2: entity xtime (structural) port map (X2xD,Y2xD);  
xt3: entity xtime (structural) port map (X1xD,Y1xD);
xt4: entity xtime (structural) port map (X0xD,Y0xD);

 


 
Z0xD <= Y0xD xor  X1xD xor A3xD;

Z2xD <= Y2xD xor  X3xD xor A1xD;

Z1xD <= Y1xD xor  X2xD xor A0xD;

Z3xD <= Y3xD xor  X0xD xor A2xD;




---------------------------------------------

Q0xD <=  A0xD xor A2xD;
Q1xD <=  A1xD xor A3xD;

xxt1: entity xxtime (structural) port map (Q0xD,R0xD);
xxt2: entity xxtime (structural) port map (Q1xD,R1xD); 

SxD <= R0xD xor R1xD;

xt5: entity xtime (structural) port map (SxD,GxD);

G0xD <= GxD xor R0xD;
G1xD <= GxD xor R1xD;

B0xD <= G0xD;
B1xD <= G1xD;

I0xD <= Z0xD xor B0xD;
I1xD <= Z1xD xor B1xD;
I2xD <= Z2xD xor B0xD;
I3xD <= Z3xD xor B1xD;

OupxDO <= I0xD & I1xD & I2xD & I3xD ;



 
end architecture ballif;