			library ieee;
			use ieee.std_logic_1164.all;

			use ieee.numeric_std.all;
			use std.textio.all;
			use work.all;

			entity kreg is
			port (
			D0xDI : in std_logic_vector (127 downto 0);
			ClkxCI : in std_logic;
			StatexDP : out std_logic_vector (127 downto 0));
			end entity kreg;


			architecture ballif of kreg is

			begin




			p_clk: process (ClkxCI)
			begin
			if ClkxCI'event and ClkxCI ='1' then
			StatexDP <= D0xDI;
			end if;

			end process p_clk;

			end architecture ballif;

lightforkaes/5_SC1_KC2_TC/src/kreg.vhd
5093465fcf8amaster

kreg.vhd
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