library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.all;


entity M10C is
port ( ClkxCI,ResxRBI : in std_logic; CxDO : inout std_logic_vector (4 downto 0) );
end entity M10C;

architecture m10 of M10C is 
signal TlxD: std_logic;
begin

TlxD <= not CxDO(0);

bit00: entity Dff_R(d01) port map (CxDO(1),ClkxCI,ResxRBI,CxDO(0));
bit01: entity Dff_R(d01) port map (CxDO(2),ClkxCI,ResxRBI,CxDO(1));
bit02: entity Dff_R(d01) port map (CxDO(3),ClkxCI,ResxRBI,CxDO(2));
bit03: entity Dff_R(d01) port map (CxDO(4),ClkxCI,ResxRBI,CxDO(3));
bit04: entity Dff_R(d01) port map (TlxD,ClkxCI,ResxRBI,CxDO(4));

end architecture m10;