Diffusion Lightweight ForkAES 7c649c3892d1

This commit contains similar changes with the previous commit Namely it…
7c649c3892d1
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Authored by ballifa on Dec 25 2020, 01:07.

Description

This commit contains similar changes with the previous commit     Namely it performs the following changes on Configuration_B implementation:

1) clock-gating (by using enabled flip-flops) is removed so that the design can be easily compiled for 5 different libraries with compile_ultra.
2) testbench is updated so that the encryption/decryption/reconstruction results are dumped into file, which simplies correctness check
3) C code for generating test vector is added
4) Makefile is added which supports GHDL (only for functional verification without any tech library)

Details

Committed

ballifa

Dec 25 2020, 01:07

Pushed

ballifa

Dec 25 2020, 01:08

Parents

R9435:e66f5cdbdf0f: This commit contains major changes in Configuration_A implementation:

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ballifa committed R9435:7c649c3892d1: This commit contains similar changes with the previous commit Namely it… (authored by ballifa).Dec 25 2020, 01:07

Changes (248)

		Path
D		Configuration_B/ED.txt
D		Configuration_B/HDL
D		Configuration_B/HDL/RTL
D		Configuration_B/HDL/RTL/AES128.vhdl~
D		Configuration_B/HDL/RTL/BIGCOL.vhdl
D		Configuration_B/HDL/RTL/COL.vhdl
V		Configuration_B/{HDL/RTL → src}/Dff_Mux.vhdl
D		Configuration_B/HDL/RTL/Dff_Mux.vhdl~
D		Configuration_B/HDL/RTL/Dff_MuxE.vhdl
D		Configuration_B/HDL/RTL/Dff_MuxE.vhdl~
V		Configuration_B/{HDL/RTL → src}/Dff_R.vhdl
D		Configuration_B/HDL/RTL/Dff_S.vhdl
D		Configuration_B/HDL/RTL/Dff_en.vhdl
V		Configuration_B/{HDL/RTL → src}/GF16_INV.vhdl
V		Configuration_B/{HDL/RTL → src}/GF16_MUL.vhdl
V		Configuration_B/{HDL/RTL → src}/GF16_SQ_SCnu.vhdl
V		Configuration_B/{HDL/RTL → src}/GF256_INV.vhdl
V		Configuration_B/{HDL/RTL → src}/GF4_MUL.vhdl
V		Configuration_B/{HDL/RTL → src}/GF4_MUL_SCLw2.vhdl
V		Configuration_B/{HDL/RTL → src}/GF4_SQ.vhdl
D		Configuration_B/HDL/RTL/GF4_ScW
V		Configuration_B/{HDL/RTL → src}/GF4_ScW.vhdl
V		Configuration_B/{HDL/RTL → src}/GF4_ScW2.vhdl
D		Configuration_B/HDL/RTL/LFSR21
D		Configuration_B/HDL/RTL/LFSR21.vhdl
D		Configuration_B/HDL/RTL/LFSR21/Dff_R.vhdl
D		Configuration_B/HDL/RTL/LFSR21/Dff_S.vhdl
D		Configuration_B/HDL/RTL/LFSR21/LFSR21.vhdl
D		Configuration_B/HDL/RTL/LFSR21/a.c
D		Configuration_B/HDL/RTL/LFSR21/a.c~
D		Configuration_B/HDL/RTL/LFSR21/a.out
D		Configuration_B/HDL/RTL/M10C.vhdl
D		Configuration_B/HDL/RTL/MC2.vhd
D		Configuration_B/HDL/RTL/MC3.vhd
D		Configuration_B/HDL/RTL/MC3.vhd~
D		Configuration_B/HDL/RTL/MC4.vhd
V		Configuration_B/{HDL/RTL → src}/MC5.vhd
V		Configuration_B/{HDL/RTL → src}/Mux21.vhdl
V		Configuration_B/{HDL/RTL → src}/Mux32_21.vhdl
V		Configuration_B/{HDL/RTL → src}/Mux8_21.vhdl
D		Configuration_B/HDL/RTL/Opreg128.vhdl
D		Configuration_B/HDL/RTL/Rcon.vhdl
D		Configuration_B/HDL/RTL/SBOX
V		Configuration_B/{HDL/RTL → src}/SBOX.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF16_INV.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF16_MUL.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF16_SQ_SCnu.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF256_INV.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF4_MUL.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF4_MUL_SCLw2.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF4_SQ.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF4_ScW
D		Configuration_B/HDL/RTL/SBOX/GF4_ScW.vhdl
D		Configuration_B/HDL/RTL/SBOX/GF4_ScW2.vhdl
D		Configuration_B/HDL/RTL/SBOX/SBOX.cr.mti
D		Configuration_B/HDL/RTL/SBOX/SBOX.mpf
D		Configuration_B/HDL/RTL/SBOX/SBOX.vhdl
D		Configuration_B/HDL/RTL/SBOX/SBOX.vhdl~
D		Configuration_B/HDL/RTL/SBOX/SBOXTB.vhdl
D		Configuration_B/HDL/RTL/SBOX/SBOXTB.vhdl~
D		Configuration_B/HDL/RTL/SBOX/a.c
D		Configuration_B/HDL/RTL/SBOX/a.c~
D		Configuration_B/HDL/RTL/SBOX/a.out
D		Configuration_B/HDL/RTL/SBOX/b.c
D		Configuration_B/HDL/RTL/SBOX/b.c~
D		Configuration_B/HDL/RTL/SBOX/ed.vec
D		Configuration_B/HDL/RTL/SBOX/inprand.vec
D		Configuration_B/HDL/RTL/SBOX/l.vec
D		Configuration_B/HDL/RTL/SBOX/vsim.wlf
D		Configuration_B/HDL/RTL/SBOX/work
D		Configuration_B/HDL/RTL/SBOX/work/_info
D		Configuration_B/HDL/RTL/SBOX/work/_vmake
D		Configuration_B/HDL/RTL/SBOX/work/gf16_inv
D		Configuration_B/HDL/RTL/SBOX/work/gf16_inv/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf16_inv/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf16_inv/gf16inv.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf16_inv/gf16inv.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf16_inv/gf16inv.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf16_inv/gf16inv.psm
D		Configuration_B/HDL/RTL/SBOX/work/gf16_mul
D		Configuration_B/HDL/RTL/SBOX/work/gf16_mul/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf16_mul/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf16_mul/gf16mul.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf16_mul/gf16mul.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf16_mul/gf16mul.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf16_mul/gf16mul.psm
D		Configuration_B/HDL/RTL/SBOX/work/gf16_sq_scnu
D		Configuration_B/HDL/RTL/SBOX/work/gf16_sq_scnu/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf16_sq_scnu/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf16_sq_scnu/gf16sqsc.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf16_sq_scnu/gf16sqsc.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf16_sq_scnu/gf16sqsc.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf16_sq_scnu/gf16sqsc.psm
D		Configuration_B/HDL/RTL/SBOX/work/gf256_inv
D		Configuration_B/HDL/RTL/SBOX/work/gf256_inv/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf256_inv/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf256_inv/gf256inv.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf256_inv/gf256inv.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf256_inv/gf256inv.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf256_inv/gf256inv.psm
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul/gf4mul.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul/gf4mul.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul/gf4mul.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul/gf4mul.psm
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul_sclw2
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul_sclw2/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul_sclw2/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul_sclw2/gf4mulsclw2.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul_sclw2/gf4mulsclw2.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul_sclw2/gf4mulsclw2.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf4_mul_sclw2/gf4mulsclw2.psm
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw/g4scw.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw/g4scw.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw/g4scw.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw/g4scw.psm
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw2
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw2/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw2/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw2/g4scw2.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw2/g4scw2.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw2/g4scw2.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf4_scw2/g4scw2.psm
D		Configuration_B/HDL/RTL/SBOX/work/gf4_sq
D		Configuration_B/HDL/RTL/SBOX/work/gf4_sq/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_sq/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_sq/g4sq.dat
D		Configuration_B/HDL/RTL/SBOX/work/gf4_sq/g4sq.dbs
D		Configuration_B/HDL/RTL/SBOX/work/gf4_sq/g4sq.prw
D		Configuration_B/HDL/RTL/SBOX/work/gf4_sq/g4sq.psm
D		Configuration_B/HDL/RTL/SBOX/work/sbox
D		Configuration_B/HDL/RTL/SBOX/work/sbox/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/sbox/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/sbox/aessbox.dat
D		Configuration_B/HDL/RTL/SBOX/work/sbox/aessbox.dbs
D		Configuration_B/HDL/RTL/SBOX/work/sbox/aessbox.prw
D		Configuration_B/HDL/RTL/SBOX/work/sbox/aessbox.psm
D		Configuration_B/HDL/RTL/SBOX/work/sboxtb
D		Configuration_B/HDL/RTL/SBOX/work/sboxtb/_primary.dat
D		Configuration_B/HDL/RTL/SBOX/work/sboxtb/_primary.dbs
D		Configuration_B/HDL/RTL/SBOX/work/sboxtb/test_sbox.dat
D		Configuration_B/HDL/RTL/SBOX/work/sboxtb/test_sbox.dbs
D		Configuration_B/HDL/RTL/SBOX/work/sboxtb/test_sbox.prw
D		Configuration_B/HDL/RTL/SBOX/work/sboxtb/test_sbox.psm
D		Configuration_B/HDL/RTL/SBOXED.vhdl
D		Configuration_B/HDL/RTL/SBOXL.vhdl
D		Configuration_B/HDL/RTL/STAGE.vhdl
D		Configuration_B/HDL/RTL/STAGE.vhdl~
D		Configuration_B/HDL/RTL/STAGEe.vhdl
D		Configuration_B/HDL/RTL/STAGEk.vhdl
D		Configuration_B/HDL/RTL/STAGEk.vhdl~
D		Configuration_B/HDL/RTL/STAGEn.vhdl
D		Configuration_B/HDL/RTL/ShiftReg128.vhdl
D		Configuration_B/HDL/RTL/aes.vhdl
D		Configuration_B/HDL/RTL/aes.vhdl~
D		Configuration_B/HDL/RTL/aes1.vhd
D		Configuration_B/HDL/RTL/aes1.vhd~
D		Configuration_B/HDL/RTL/aes20.vhdl
D		Configuration_B/HDL/RTL/aes20.vhdl~
D		Configuration_B/HDL/RTL/aes_small.vhdl
D		Configuration_B/HDL/RTL/aes_small.vhdl~
D		Configuration_B/HDL/RTL/aescg.vhd
D		Configuration_B/HDL/RTL/aesv2.vhdl
D		Configuration_B/HDL/RTL/aesv2_tb.vhdl
D		Configuration_B/HDL/RTL/aesv3.vhdl
D		Configuration_B/HDL/RTL/aesv3b.vhdl
D		Configuration_B/HDL/RTL/aesv3f.vhdl
D		Configuration_B/HDL/RTL/cgate.vhd
V		Configuration_B/{HDL/RTL → src}/cgate1.vhd
D		Configuration_B/HDL/RTL/comp.vhd
D		Configuration_B/HDL/RTL/eff.vhd
D		Configuration_B/HDL/RTL/eff1.vhd
V		Configuration_B/{HDL/RTL → src}/ereg.vhd
D		Configuration_B/HDL/RTL/forkaesv0.vhdl
D		Configuration_B/HDL/RTL/forkaesv00.vhdl
D		Configuration_B/HDL/RTL/forkaesv01.vhdl
D		Configuration_B/HDL/RTL/forkaesv02.vhdl
V		Configuration_B/{HDL/RTL → src}/forkaesv10.vhdl
D		Configuration_B/HDL/RTL/mixcolumn.vhd
D		Configuration_B/HDL/RTL/mulenc.vhd
D		Configuration_B/HDL/RTL/to.c
V		Configuration_B/{HDL/RTL → src}/xtime.vhd
V		Configuration_B/{HDL/RTL → src}/xxtime.vhd
D		Configuration_B/HDL/TBENCH
D		Configuration_B/HDL/TBENCH/AES128TB.vhdl.bak
D		Configuration_B/HDL/TBENCH/PresentSerialTB.vhdl
D		Configuration_B/HDL/TBENCH/PresentSerialTB.vhdl.bak
D		Configuration_B/HDL/TBENCH/PresentTB.vhdl
D		Configuration_B/HDL/TBENCH/SBOXTB.vhdl
D		Configuration_B/HDL/TBENCH/SBOXTB.vhdl.bak
D		Configuration_B/HDL/TBENCH/aes_tb.vhdl
D		Configuration_B/HDL/TBENCH/aes_tb.vhdl.bak
D		Configuration_B/HDL/TBENCH/aes_tb.vhdl~
D		Configuration_B/HDL/TBENCH/aesv2_tb.vhdl
D		Configuration_B/HDL/TBENCH/forkv0_tb.vhdl
D		Configuration_B/HDL/TBENCH/forkv0_tb.vhdl.bak
V		Configuration_B/{HDL/TBENCH → src}/forkv1_tb.vhdl
D		Configuration_B/Key.txt
D		Configuration_B/Key8.txt
A		Configuration_B/Makefile
D		Configuration_B/Mode.txt
D		Configuration_B/PT.txt
D		Configuration_B/PT8.txt
D		Configuration_B/gen.c
D		Configuration_B/post.sh
D		Configuration_B/power_lp.tcl
V		Configuration_B/{ → scripts}/saif.cmd
D		Configuration_B/script.tcl
A	(dir)	Configuration_B/scripts/
A		Configuration_B/scripts/analyze.sh
A		Configuration_B/scripts/compile.tcl
A		Configuration_B/scripts/power.tcl
V		Configuration_B/{scripts ← }/saif.cmd
A		Configuration_B/scripts/verify.sh
A	(dir)	Configuration_B/src/
V		Configuration_B/{src ← HDL/RTL}/Dff_Mux.vhdl
V		Configuration_B/{src ← HDL/RTL}/Dff_R.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF16_INV.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF16_MUL.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF16_SQ_SCnu.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF256_INV.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF4_MUL.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF4_MUL_SCLw2.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF4_SQ.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF4_ScW.vhdl
V		Configuration_B/{src ← HDL/RTL}/GF4_ScW2.vhdl
V		Configuration_B/{src ← HDL/RTL}/MC5.vhd
V		Configuration_B/{src ← HDL/RTL}/Mux21.vhdl
V		Configuration_B/{src ← HDL/RTL}/Mux32_21.vhdl
V		Configuration_B/{src ← HDL/RTL}/Mux8_21.vhdl
V		Configuration_B/{src ← HDL/RTL}/SBOX.vhdl
A		Configuration_B/src/STAGE.vhdl
A		Configuration_B/src/STAGEn.vhdl
V		Configuration_B/{src ← HDL/RTL}/cgate1.vhd
A		Configuration_B/src/eff1.vhd
V		Configuration_B/{src ← HDL/RTL}/ereg.vhd
V		Configuration_B/{src ← HDL/RTL}/forkaesv10.vhdl
A		Configuration_B/src/forkv0_tb.vhdl
V		Configuration_B/{src ← HDL/TBENCH}/forkv1_tb.vhdl
V		Configuration_B/{src ← HDL/RTL}/xtime.vhd
V		Configuration_B/{src ← HDL/RTL}/xxtime.vhd
A	(dir)	Configuration_B/test_vectors/
A		Configuration_B/test_vectors/case_generator.c