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lightforkaes/Configuration_A/src/forkv0_tb.vhdl
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forkv0_tb.vhdl
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.all;
entity aes_tb is
end aes_tb;
architecture tb of aes_tb is
signal InxD : std_logic_vector (7 downto 0);
signal KeyxD : std_logic_vector (7 downto 0);
signal TweakxD : std_logic_vector (7 downto 0);
signal OutxD : std_logic_vector (7 downto 0);
signal ModexS : std_logic_vector (1 downto 0);
signal ClkxC : std_logic;
signal ResetxRB : std_logic;
signal OpxS : std_logic;
signal cont_flag : boolean := true;
constant clkphase : time := 50 ns;
constant resetactivetime : time := 25 ns;
component aes
port(
InxDI : in std_logic_vector(7 downto 0);
KeyxDI : in std_logic_vector(7 downto 0);
TweakxDI : in std_logic_vector(7 downto 0);
OutxDO : out std_logic_vector(7 downto 0);
ModexSI : in std_logic_vector(1 downto 0);
ResetxRBI : in std_logic;
ClkxCI : in std_logic;
OpxSO : out std_logic
);
end component;
begin
mut: aes
port map (
InxDI => InxD,
KeyxDI => KeyxD,
TweakxDI => TweakxD,
OutxDO => OutxD,
ModexSI => ModexS,
ResetxRBI => ResetxRB,
ClkxCI => ClkxC,
OpxSO => OpxS
);
Tb_clkgen : process
begin
if cont_flag then
ClkxC <= '1';
wait for clkphase;
ClkxC <= '0';
wait for clkphase;
else
wait;
end if;
end process Tb_clkgen;
B1 : block
begin
Tb_stimappli : process
variable line_var : line;
variable temp_k : std_logic_vector(127 downto 0);
variable temp_p : std_logic_vector(127 downto 0);
variable temp_t : std_logic_vector(63 downto 0);
variable tmp_out : std_logic_vector(127 downto 0);
variable temp_ed : std_logic_vector(3 downto 0);
file infile : text;
file outfile : text;
procedure dump_to_file is
begin
for i in 0 to 15 loop
wait for 2*clkphase;
tmp_out(127 - 8*i downto 120 - 8*i) := OutxD;
end loop;
hwrite(line_var, tmp_out);
writeline(outfile, line_var);
end procedure;
begin
cont_flag <= true;
file_open(infile, "Testinput.txt", read_mode);
file_open(outfile, "tb_output.txt", write_mode);
ResetxRB <= '0';
InxD <= (others => '0');
KeyxD <= (others => '0');
TweakxD <= (others => '0');
ModexS <= "00";
wait for resetactivetime;
ResetxRB <= '1';
appli_loop : while not (endfile(infile)) loop
readline(infile, line_var);
hread(line_var, temp_p);
readline(infile, line_var);
hread(line_var, temp_k);
readline(infile,line_var);
hread(line_var, temp_t);
readline(infile,line_var);
hread(line_var, temp_ed);
ModexS <= temp_ed(1 downto 0);
for i in 15 downto 0 loop
KeyxD <= temp_k(8*i+7 downto 8*i);
InxD <= temp_p(8*i+7 downto 8*i);
if i >7 then
TweakxD <= temp_t(8*i-57 downto 8*i-64);
else
TweakxD <= "00000000";
end if;
wait for 2*clkphase;
end loop;
if ModexS = "00" then
wait for 2*clkphase*214 - resetactivetime;
dump_to_file;
wait for 2*clkphase*392;
dump_to_file;
elsif ModexS = "01" then
wait for 2*clkphase*294 - resetactivetime;
dump_to_file;
elsif ModexS = "10" then
wait for 2*clkphase*392 - resetactivetime;
dump_to_file;
end if;
ResetxRB <= '0';
wait for resetactivetime;
ResetxRB <= '1';
end loop appli_loop;
wait until rising_edge(ClkxC);
ResetxRB <= '0';
file_close(infile);
file_close(outfile);
cont_flag <= false;
wait;
end process Tb_stimappli;
end block;
end tb;
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